US4769558A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit clock bus layout delay system
Assignee: MARHOEFER LAURENCE J
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Filing: 1986-07-09
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Granted: 1988-09-06
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Expires: 2006-07-09
Abstract
Abstract A clock bus system fabricated on an integrated circuit for distributing a train of clock pulses to circuit elements on the integrated circuit. An input terminal is connected to receive a train of clock pulses. All of the circuit elements are circumscribed by a clock bus which is also coupled to each of the circuit elements. A plurality of distribution legs which include clock bus drivers are coupled to the input terminal by conductors and provide the train of clock pulses to the clock bus at spaced-apart locations. The distribution legs coupled to the input terminal by shorter conductors include delay elements for delaying the clock pulse train by time periods corresponding to the delay inherent in longer conductors. The clock pulse trains provided to the clock bus by the distribution legs are thereby synchronized with respect to each other.
Inventors
- 👤 Randall E. Bach
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 11:12
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/10
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
162 words
An integrated circuit, including: terminal means for receiving a train of clock pulses; a plurality of circuit elements; clock bus means substantially circumscribing the circuit elements for propagating the train of clock pulses, wherein the circuit elements are coupled to the clock bus means; a plurality of distribution legs, each coupling the train of clock pulses to the clock bus means at spaced-apart locations; conductors coupling the distribution legs to the terminal means, each conductor characterized by a conductor delay period, and wherein at least some of the conductor delay periods differ; and delay means associated with each of at least some of the distribution legs, for delaying the clock pulse train by a predetermined time delay period, wherein the predetermined time delay period of the delay means corresponds to a difference between a greatest conductor delay period and the conductor delay period of the conductor coupling the clock pulse train to the distribution leg with which the delay means is associated.
Claim 2
Dependent Claim
162 words
An integrated circuit, including: terminal means for receiving a train of clock pulses; a plurality of circuit elements; clock bus means substantially circumscribing the circuit elements for propagating the train of clock pulses, wherein the circuit elements are coupled to the clock bus means; a plurality of distribution legs, each coupling the train of clock pulses to the clock bus means at spaced-apart locations; conductors coupling the distribution legs to the terminal means, each conductor characterized by a conductor delay period, and wherein at least some of the conductor delay periods differ; and delay means associated with each of at least some of the distribution legs, for delaying the clock pulse train by a predetermined time delay period, wherein the predetermined time delay period of the delay means corresponds to a difference between a greatest conductor delay period and the conductor delay period of the conductor coupling the clock pulse train to the distribution leg with which the delay means is associated.
Claim 3
Dependent Claim
19 words
The integrated circuit of claim 1 wherein the clock bus means is closed and completely circumscribes the circuit elements.
Claim 4
Dependent Claim
39 words
The integrated circuit of claim 1 wherein the plurality of distribution legs consist of first, second, third, and fourth distribution legs coupling the train of clock pulses to the clock bus means at locations spaced apart by approximately 90°.
Claim 5
Dependent Claim
113 words
The integrated circuit of claim 13 wherein: the conductors consist of a first conductor coupling the first distribution leg to the terminal means, a second conductor coupling the second distribution leg to the terminal means, a third conductor coupling the third distribution leg to the second distribution leg, and a fourth conductor coupling the fourth distribution leg to the first distribution leg; the first and second conductors are approximately equal in length; the third and fourth conductors are approximately equal in length; and the delay means of the first and second distribution legs delay the clock pulse train by a delay period corresponding to a delay inherent in the third and fourth conductors.
Claim 6
Dependent Claim
15 words
The integrated circuit of claim 1 wherein each distribution leg includes a clock bus driver.
Claim 7
Dependent Claim
14 words
The integrated circuit of claim 1 wherein the distribution means includes clock bus drivers.
References Cited (Backward Citations)
US3171981A
Cited
US3418498A
Cited
US3633113A
Cited
US3725793A
Cited
US3753012A
Cited
US4208724A
Cited
US4241418A
Cited
US4419739A
Cited
US4321687A
Cited
US4414637A
Cited
US4447876A
Cited
US4523106A
Cited
US4507574A
Cited
US4412342A
Cited
US4482826A
Cited
US4479216A
Cited
US4572572A
Cited
US4639615A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-09-06 | 1992-03-07 | 1992-09-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-09-06 | 1996-03-07 | 1996-09-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-09-06 | 2000-03-07 | 2000-09-06 | $7700.00 | Window Closed / Lapsed |