Decentralized generation of synchronized clock control signals having dynamically selectable periods

Claim 1

Apparatus for generating clock control signals in a microprogrammed digital processing system having a plurality of circuitized chips, each of the chips having local switching points therein, said apparatus comprising: (a) first circuit means, located on each chip requiring same, for generating, when started, a fixed number of clock timing signals; (b) master clock circuit means, operatively coupled to each of said first circuit means, for generating clock signals and for synchronously driving said first circuit means with respect to each other; (c) second circuit means, operatively coupled to said first circuit means, for receiving and decoding operation codes of the micro instructions and for deriving OP-CODE control signals therefrom for use, in conjunction with said clock signals, in developing clock control signals for application to the switching points of each of the individual chips; and (d) third circuit means responsive to said OP-CODES and operatively coupled to each of said first circuit means for generating a reset signal therefor to reset each of said first circuit means to their initial timing interval whenever the need arises at any point within a timing cycle to reduce the maximum number of clock timing signals provided per cycle by said first circuit means.