US5640547A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices
Assignee: Renesas Electronics Corp
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Filing: 1994-07-26
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Granted: 1997-06-17
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Expires: 2014-07-26
Abstract
Abstract An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K 1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K 1 , and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K 1 .
Inventors
- 👤 Takashi Hotta
- 👤 Kozaburo Kurita
- 👤 Masahiro Iwamura
- 👤 Hideo Maejima
- 👤 Shigeya Tanaka
- 👤 Tadaaki Bandoh
- 👤 Yasuhiro Nakatsuka
- 👤 Kazuo Kato
- 👤 Sin-ichi Sinoda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 07:30
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/06; H; H03; H03K; H03K5/00; H03K5/156; H03K5/1565; G06F1/08; G06F1/10; H03K17/00; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/096; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/18; H10; H10D; H10D84/00
Claims Analysis
Total Claims: 34
Claim 1
Independent Claim
179 words
A data processing apparatus including a plurality of logic circuit blocks for performing operations on data and a clock generator for generating a clock signal for use by said logic circuit blocks, said clock generator and said data processing apparatus being fabricated on a single semiconductor substrate and said clock generator being arranged on said semiconductor substrate in a manner to reduce the effect of noise, generated by said clock generator, on the operations of said logic circuit blocks, said clock generator comprising: a plurality of clock signal supplying lines connected to said logic circuit blocks; clock signal supplying means for supplying a clock signal; and a plurality of clock drivers being disposed along edges of at least two sides of said semiconductor substrate to reduce the effect of noise, generated by said clock generator, on the operations of said logic circuit blocks, said clock drivers connecting said clock supplying means to said clock supplying lines, and supplying said clock signal provided by said clock signal supplying means to said logic circuit blocks via said clock signal supplying lines.
Claim 2
Dependent Claim
179 words
A data processing apparatus including a plurality of logic circuit blocks for performing operations on data and a clock generator for generating a clock signal for use by said logic circuit blocks, said clock generator and said data processing apparatus being fabricated on a single semiconductor substrate and said clock generator being arranged on said semiconductor substrate in a manner to reduce the effect of noise, generated by said clock generator, on the operations of said logic circuit blocks, said clock generator comprising: a plurality of clock signal supplying lines connected to said logic circuit blocks; clock signal supplying means for supplying a clock signal; and a plurality of clock drivers being disposed along edges of at least two sides of said semiconductor substrate to reduce the effect of noise, generated by said clock generator, on the operations of said logic circuit blocks, said clock drivers connecting said clock supplying means to said clock supplying lines, and supplying said clock signal provided by said clock signal supplying means to said logic circuit blocks via said clock signal supplying lines.
Claim 3
Dependent Claim
28 words
A data processing apparatus according to claim 1, wherein the outputs of said plurality of clock drivers are interconnected to each other by said clock signal supplying lines.
Claim 4
Dependent Claim
56 words
A data processing apparatus according to claim 2, wherein said clock signal supplying lines include a line in the form of a loop which surrounds at least some of said plurality of logic circuit blocks on said semiconductor substrate such that said clock drivers are positioned between edges of said substrate and said logic circuit blocks.
Claim 5
Dependent Claim
15 words
A data processing apparatus according to claim 1, wherein said clock drivers are tri-state buffers.
Claim 6
Dependent Claim
162 words
A data processing apparatus including a plurality of logic devices for performing operations on data and a clock generator for generating a clock signal for use by said logic devices, said clock generator and said data processing apparatus being fabricated on a single semiconductor substrate and said clock generator being arranged on said semiconductor substrate in a manner to reduce the effect of noise, generated by said clock generator, on the operations of said logic devices, said clock generator comprising: a network for interconnecting said logic devices to each other and receiving a clock signal, said network being disposed within a predetermined area of said semiconductor substrate; and a plurality of clock drivers being disposed along an edge of said single semiconductor substrate outside of said predetermined area to reduce the effect of noise, generated by said clock generator, on the operations of said logic devices, said clock drivers supply a clock signal to said plurality of logic devices via said network.
Claim 7
Dependent Claim
162 words
A data processing apparatus including a plurality of logic devices for performing operations on data and a clock generator for generating a clock signal for use by said logic devices, said clock generator and said data processing apparatus being fabricated on a single semiconductor substrate and said clock generator being arranged on said semiconductor substrate in a manner to reduce the effect of noise, generated by said clock generator, on the operations of said logic devices, said clock generator comprising: a network for interconnecting said logic devices to each other and receiving a clock signal, said network being disposed within a predetermined area of said semiconductor substrate; and a plurality of clock drivers being disposed along an edge of said single semiconductor substrate outside of said predetermined area to reduce the effect of noise, generated by said clock generator, on the operations of said logic devices, said clock drivers supply a clock signal to said plurality of logic devices via said network.
Claim 8
Dependent Claim
40 words
A data processing apparatus according to claim 5, wherein the outputs of said plurality of clock drivers are interconnected to each other by clock signal supplying lines, said clock signal supplying lines are interconnected to each other forming said network.
Claim 9
Dependent Claim
38 words
A data processing apparatus according to claim 6, wherein said clock signal supplying lines include a line in the form of a loop which surrounds at least some of said plurality of logic devices on said semiconductor substrate.
Claim 10
Dependent Claim
15 words
A data processing apparatus according to claim 5, wherein said clock drivers are tri-state buffers.
Claim 11
Dependent Claim
22 words
A data processing apparatus according to claim 5, wherein said network includes connectors which are interconnected to each other forming a ladder.
Claim 12
Dependent Claim
25 words
A data processing apparatus according to claim 5, wherein said clock drivers are disposed along edges of at least two sides of said semiconductor substrate.
Claim 13
Dependent Claim
192 words
A data processing apparatus including a plurality of logic circuit blocks for performing operations on data and a clock generator for generating a clock signal for use by said logic circuit blocks, said clock generator and said data processing apparatus being fabricated on a single semiconductor substrate and said clock generator being arranged on said semiconductor substrate in a manner to reduce the effect of noise, generated by said clock generator, on the operations of said logic circuit blocks, said clock generator comprising: a plurality of clock signal supplying lines which are interconnected to each other forming a ladder structure on said semiconductor substrate, said logic circuit blocks being connected to said clock signal supplying lines; clock signal supplying means for supplying a clock signal; and a plurality of clock drivers, disposed along an edge of said semiconductor substrate to reduce the effect of noise, generated by said clock generator, on the operations of said logic circuit blocks, said clock drivers being connected to said clock signal supplying lines, and supplying said clock signal provided by said clock signal supplying means to said logic circuit blocks via said clock signal supplying line.
Claim 14
Dependent Claim
192 words
A data processing apparatus including a plurality of logic circuit blocks for performing operations on data and a clock generator for generating a clock signal for use by said logic circuit blocks, said clock generator and said data processing apparatus being fabricated on a single semiconductor substrate and said clock generator being arranged on said semiconductor substrate in a manner to reduce the effect of noise, generated by said clock generator, on the operations of said logic circuit blocks, said clock generator comprising: a plurality of clock signal supplying lines which are interconnected to each other forming a ladder structure on said semiconductor substrate, said logic circuit blocks being connected to said clock signal supplying lines; clock signal supplying means for supplying a clock signal; and a plurality of clock drivers, disposed along an edge of said semiconductor substrate to reduce the effect of noise, generated by said clock generator, on the operations of said logic circuit blocks, said clock drivers being connected to said clock signal supplying lines, and supplying said clock signal provided by said clock signal supplying means to said logic circuit blocks via said clock signal supplying line.
Claim 15
Dependent Claim
28 words
A data processing apparatus according to claim 11, wherein the outputs of said plurality of clock drivers are interconnected to each other by said clock signal supplying lines.
Claim 16
Dependent Claim
35 words
A data processing apparatus according to claim 11, wherein said clock signal supplying lines includes lines forming a loop which surrounds at least some of said plurality of logic circuit blocks on said semiconductor substrate.
Claim 17
Dependent Claim
15 words
A data processing apparatus according to claim 11, wherein said clock drivers are tri-state buffers.
Claim 18
Dependent Claim
190 words
A data processing apparatus having a plurality of logic circuit blocks for performing operations on data and a clock generator for generating a clock signal for use by said logic circuit blocks, said clock generator and said data processing apparatus being fabricated on a single semiconductor substrate and said clock generator being arranged on said semiconductor substrate in a manner to simplify layout of circuits including said data processing apparatus and said clock generator on said semiconductor substrate, said clock generator comprising: a plurality of clock signal supplying lines, each clock signal supplying line is connected to at least one of said logic circuit blocks; clock signal supplying means for supplying a clock signal; and a plurality of clock drivers being disposed along edges of at least two sides of said semiconductor substrate to simplify the layout of circuits including said data processing apparatus and said clock generator on said semiconductor substrate, said clock drivers connecting said clock signal supplying means to said clock signal supplying lines, and supplying said clock signal, provided by said clock signal supplying means, to said logic circuit blocks via said clock signal supplying lines.
Claim 19
Dependent Claim
190 words
A data processing apparatus having a plurality of logic circuit blocks for performing operations on data and a clock generator for generating a clock signal for use by said logic circuit blocks, said clock generator and said data processing apparatus being fabricated on a single semiconductor substrate and said clock generator being arranged on said semiconductor substrate in a manner to simplify layout of circuits including said data processing apparatus and said clock generator on said semiconductor substrate, said clock generator comprising: a plurality of clock signal supplying lines, each clock signal supplying line is connected to at least one of said logic circuit blocks; clock signal supplying means for supplying a clock signal; and a plurality of clock drivers being disposed along edges of at least two sides of said semiconductor substrate to simplify the layout of circuits including said data processing apparatus and said clock generator on said semiconductor substrate, said clock drivers connecting said clock signal supplying means to said clock signal supplying lines, and supplying said clock signal, provided by said clock signal supplying means, to said logic circuit blocks via said clock signal supplying lines.
Claim 20
Dependent Claim
40 words
A data processing apparatus according to claim 15, wherein the outputs of each of a plurality of pairs of clock drivers of said plurality of clock drivers are interconnected to each other by one of said clock signal supplying lines.
Claim 21
Dependent Claim
56 words
A data processing apparatus according to claim 16, wherein said clock signal supplying lines include a line in the form of a loop which surrounds at least some of said plurality of logic circuit blocks on said semiconductor substrate such that said clock drivers are positioned between edges of said substrate and said logic circuit blocks.
Claim 22
Dependent Claim
15 words
A data processing apparatus according to claim 15, wherein said clock drivers are tri-state buffers.
Claim 23
Dependent Claim
167 words
A data processing apparatus having a plurality of logic devices for performing operations on data and a clock generator for generating a clock signal for use by said logic devices, said clock generator and said data processing apparatus being fabricated on a single semiconductor substrate and said clock generator being arranged on said semiconductor substrate in a manner to simplify layout of circuits including said data processing apparatus and said clock generator on said semiconductor substrate, said clock generator comprising: a network for interconnecting said logic devices to each other and receiving a clock signal, said network being disposed within a predetermined area of said semiconductor substrate; and a plurality of clock drivers being disposed along an edge of said single semiconductor substrate in another predetermined area separate from said predetermined area to simplify the layout of circuits including said data processing apparatus and said clock generator on said semiconductor substrate, said clock drivers supplies a clock signal to said plurality of logic devices via said network.
Claim 24
Dependent Claim
167 words
A data processing apparatus having a plurality of logic devices for performing operations on data and a clock generator for generating a clock signal for use by said logic devices, said clock generator and said data processing apparatus being fabricated on a single semiconductor substrate and said clock generator being arranged on said semiconductor substrate in a manner to simplify layout of circuits including said data processing apparatus and said clock generator on said semiconductor substrate, said clock generator comprising: a network for interconnecting said logic devices to each other and receiving a clock signal, said network being disposed within a predetermined area of said semiconductor substrate; and a plurality of clock drivers being disposed along an edge of said single semiconductor substrate in another predetermined area separate from said predetermined area to simplify the layout of circuits including said data processing apparatus and said clock generator on said semiconductor substrate, said clock drivers supplies a clock signal to said plurality of logic devices via said network.
Claim 25
Dependent Claim
55 words
A data processing apparatus according to claim 19, wherein the outputs of each of a plurality of pairs of clock drivers of said plurality of clock drivers are interconnected to each other by one of a plurality of clock signal supplying lines, said clock signal supplying lines are interconnected to each other forming said network.
Claim 26
Dependent Claim
38 words
A data processing apparatus according to claim 20, wherein said clock signal supplying lines include a line in the form of a loop which surrounds at least some of said plurality of logic devices on said semiconductor substrate.
Claim 27
Dependent Claim
15 words
A data processing apparatus according to claim 19, wherein said clock drivers are tri-state buffers.
Claim 28
Dependent Claim
22 words
A data processing apparatus according to claim 19, wherein said network includes connectors which are interconnected to each other forming a ladder.
Claim 29
Dependent Claim
25 words
A data processing apparatus according to claim 19, wherein said clock drivers are disposed along edges of at least two sides of said semiconductor substrate.
Claim 30
Dependent Claim
195 words
A data processing apparatus having a plurality of logic circuit blocks for performing operations on data and a clock generator for generating a clock signal for use by said logic circuit blocks, said clock generator and said data processing apparatus being fabricated on a single semiconductor substrate and said clock generator being arranged on said semiconductor substrate in a manner to simplify layout of circuits including said data processing apparatus and said clock generator on said semiconductor substrate, said clock generator comprising: a plurality of clock signal supplying lines which are interconnected to each other forming a ladder structure on said semiconductor substrate, each clock signal supplying lines being connected to at least one of said logic circuit blocks; clock signal supplying means for supplying a clock signal; and a plurality of clock drivers disposed along an edge of said semiconductor substrate to simplify the layout of circuits including said data processing apparatus and said clock apparatus on said semiconductor substrate, said clock drivers being connected to said clock signal supplying lines, and supplying said clock signal provided by said clock signal supplying means to said logic circuit blocks via said clock signal supplying lines.
Claim 31
Dependent Claim
195 words
A data processing apparatus having a plurality of logic circuit blocks for performing operations on data and a clock generator for generating a clock signal for use by said logic circuit blocks, said clock generator and said data processing apparatus being fabricated on a single semiconductor substrate and said clock generator being arranged on said semiconductor substrate in a manner to simplify layout of circuits including said data processing apparatus and said clock generator on said semiconductor substrate, said clock generator comprising: a plurality of clock signal supplying lines which are interconnected to each other forming a ladder structure on said semiconductor substrate, each clock signal supplying lines being connected to at least one of said logic circuit blocks; clock signal supplying means for supplying a clock signal; and a plurality of clock drivers disposed along an edge of said semiconductor substrate to simplify the layout of circuits including said data processing apparatus and said clock apparatus on said semiconductor substrate, said clock drivers being connected to said clock signal supplying lines, and supplying said clock signal provided by said clock signal supplying means to said logic circuit blocks via said clock signal supplying lines.
Claim 32
Dependent Claim
40 words
A data processing apparatus according to claim 25, wherein the outputs of each of a plurality of pairs of clock drivers of said plurality of clock drivers are interconnected to each other by one of said clock signal supplying lines.
Claim 33
Dependent Claim
35 words
A data processing apparatus according to claim 25, wherein said clock signal supplying lines includes lines forming a loop which surrounds at least some of said plurality of logic circuit blocks on said semiconductor substrate.
Claim 34
Dependent Claim
15 words
A data processing apparatus according to claim 25, wherein said clock drivers are tri-state buffers.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-06-16 | 2000-12-16 | 2001-06-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-06-16 | 2004-12-16 | 2005-06-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-06-16 | 2008-12-16 | 2009-06-17 | $7700.00 | Window Closed / Lapsed |