US5559477A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Pulse generator having controlled delay to control duty cycle
Assignee: Silicon Laboratories Inc
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Filing: 1995-09-15
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Granted: 1996-09-24
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Expires: 2015-09-15
Abstract
Abstract Five CMOS inverters are connected in a series ring to form an oscillator. Current to the inverters is controlled to establish gate delays of the inverters and thereby determine a frequency of oscillation of the oscillator. The oscillator is included in a phase locked loop where the gate delay of the inverters is selected by selecting the value of a frequency divider of the phase locked loop. The selected delay is used to form a train of pulses with a desired duty cycle.
Inventors
- 👤 Orhan Tozun
- 👤 Chit-Ah Mak
- 👤 Werner Hoeft
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 03:51
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/0805; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/03; H03K3/0315; H03K5/00; H03K5/156; H03K5/1565; H03L7/099; H03L7/0995
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
191 words
A circuit for generating a train of pulses having a selectable duty cycle, comprising: a source of pulses comprising: an odd number of similar inverters connected in a series ring to form an oscillator; and delay means for causing said inverters to have a selectable gate delay, said delay means comprising: an odd number of voltage controlled current sources equal in number to said inverters and respectively connected to P channel current inputs thereof; and an odd number of voltage controlled current sources equal in number to said inverters and respectively connected to N channel current inputs thereof, said current sources having respective control inputs connected to a source of a control voltage, said current sources each providing a current proportional to said control voltage whereby said inverters and said current sources form a voltage controlled oscillator (VCO), the inputs thereof being controlled inputs; a gate having an input connected to said pulse source wherein said gate is an inverter of said oscillator; means for causing said gate to have a selectable gate delay; and means for logically combining the output of said pulse source with the output of said gate.
Claim 2
Dependent Claim
191 words
A circuit for generating a train of pulses having a selectable duty cycle, comprising: a source of pulses comprising: an odd number of similar inverters connected in a series ring to form an oscillator; and delay means for causing said inverters to have a selectable gate delay, said delay means comprising: an odd number of voltage controlled current sources equal in number to said inverters and respectively connected to P channel current inputs thereof; and an odd number of voltage controlled current sources equal in number to said inverters and respectively connected to N channel current inputs thereof, said current sources having respective control inputs connected to a source of a control voltage, said current sources each providing a current proportional to said control voltage whereby said inverters and said current sources form a voltage controlled oscillator (VCO), the inputs thereof being controlled inputs; a gate having an input connected to said pulse source wherein said gate is an inverter of said oscillator; means for causing said gate to have a selectable gate delay; and means for logically combining the output of said pulse source with the output of said gate.
Claim 3
Dependent Claim
12 words
The circuit of claim 1 wherein said gate is of CMOS construction.
Claim 4
Dependent Claim
48 words
The circuit of claim 1 wherein said means for causing comprises a pair of voltage controlled current sources respectively connected to a P channel current input and an N channel current input of said gate, said current sources having their control lines connected to said control voltage source.
Claim 5
Dependent Claim
55 words
The circuit of claim 1 wherein said gate is of CMOS construction and said means for causing comprises a pair of voltage controlled current sources respectively connected to a P channel current input and an N channel current input of said gate, said current sources having their control lines connected to said control voltage source.
Claim 6
Dependent Claim
27 words
The circuit of claim 1 wherein said pulse source additionally comprises a frequency divider having an input connected to the output of said inverter of said oscillator.
References Cited (Backward Citations)
US5039893A
Cited
US4797585A
Cited
US5119045A
Cited
US5231313A
Cited
US5302919A
Cited
US5068628A
Cited
US5061907A
Cited
US5136260A
Cited
US5175452A
Cited
US5347232A
Cited
US5302920A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-09-24 | 2000-03-25 | 2000-09-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-09-24 | 2004-03-25 | 2004-09-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-09-24 | 2008-03-25 | 2008-09-24 | $7700.00 | Window Closed / Lapsed |