US5570053A
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Method and apparatus for averaging clock skewing in clock distribution network
Assignee: Renesas Electronics America Inc
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Filing: 1994-09-26
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Granted: 1996-10-29
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Expires: 2014-09-26
Abstract
Abstract A system clock signal is delivered to a plurality of load devices by means of a common loop filter and delay line and a plurality of phase detectors and charge pumps each associated to a different load. The delay line provides a plurality of substantially identical phase corrected clock signals, each clock signal being coupled to the associated load device via an associated conductor member. In one embodiment, each conductor member comprises a loop consisting of a pair of conductors having substantially identical path lengths. The phase adjusted clock signals on the proximal end of the outbound conductor are coupled back as a first feedback signal to one input of the associated phase detector. Another feedback signal comprises the clock signal returned from the device node along the second conductor of the pair. A third input to the phase detector is the system input clock signal, which is also coupled to a reference input of the delay line. Each phase detector/charge pump combination generates a phase error correction signal corresponding to any delay associated with a given loop and device. The plurality of phase error correction signals are averaged in a loop filter and delay line, so that each phase corrected clock signal output from the delay line contains the average correction for all of the delays. In an alternate embodiment, the return loop is eliminated so that a single feedback signal representative of the delay induced by each load device is coupled to one input of a conventional two input phase detector. In this embodiment, the load effect on the distributed clock signals is averaged out.
Inventors
- 👤 Ashraf K. Takla
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 01:31
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/10; H; H03; H03K; H03K5/00; H03K5/15; H03K5/15013; H03K5/1506; H03L; H03L7/00; H03L7/06; H03L7/07; H03L7/08; H03L7/081; H03L7/0812; H03L7/0816; H03L7/085; H03L7/087; H03L7/089; H03L7/0891
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
188 words
A clock deskewing circuit for synchronizing a clock signal at destination loads with a system clock by averaging delay variations along a plurality of clock distribution paths, said circuit comprising: a first input terminal for receiving a system clock signal; a plurality of clock signal conductor members each having a proximal end and a distal end for providing a phase adjusted clock signal to an associated load device; a plurality of phase error correction signal generating circuits each coupled to said first input terminal and to the proximal ends of said plurality of clock signal conductor members for generating a plurality of phase error correction signals each corresponding to the associated load device and each providing a phase correction for any delay associated thereto; and averaging means coupled to said plurality of phase error correction signal generator circuits, said first input terminal and said plurality of clock signal conductor members for generating a plurality of substantially identical phase adjusted clock signals each coupled to a different one of said plurality of clock signal conductor members and each incorporating an average of the plurality of phase error correction signals.
Claim 2
Dependent Claim
188 words
A clock deskewing circuit for synchronizing a clock signal at destination loads with a system clock by averaging delay variations along a plurality of clock distribution paths, said circuit comprising: a first input terminal for receiving a system clock signal; a plurality of clock signal conductor members each having a proximal end and a distal end for providing a phase adjusted clock signal to an associated load device; a plurality of phase error correction signal generating circuits each coupled to said first input terminal and to the proximal ends of said plurality of clock signal conductor members for generating a plurality of phase error correction signals each corresponding to the associated load device and each providing a phase correction for any delay associated thereto; and averaging means coupled to said plurality of phase error correction signal generator circuits, said first input terminal and said plurality of clock signal conductor members for generating a plurality of substantially identical phase adjusted clock signals each coupled to a different one of said plurality of clock signal conductor members and each incorporating an average of the plurality of phase error correction signals.
Claim 3
Dependent Claim
83 words
The invention of claim 1 wherein said plurality of phase error correction signal generating circuits each includes a phase detector circuit having a first input for receiving the system clock signal, a second input coupled to the corresponding clock signal conductor member for receiving a feedback signal representative of the delay associated to the load device, and an output; and a charge pump having an input coupled to the output of said phase detector circuit and an output coupled to said averaging means.
Claim 4
Dependent Claim
73 words
The invention of claim 1 wherein said averaging means includes a loop filter having an input coupled to said plurality of phase error correction signal generating circuits, and an output; and a delay line having a first input coupled to the output of said loop filter, a second input coupled to said first input terminal and a plurality of outputs each coupled to a different one of said plurality of signal conducting members.
Claim 5
Dependent Claim
140 words
The invention of claim 1 wherein said plurality of clock signal conductor members each comprises a pair of conductors joined at the distal end with each conductor having a path length and a proximal end, the proximal end of one conductor in a given pair being coupled to said averaging means to receive one of said plurality of substantially identical phase adjusted clock signals, said proximal end also being coupled to the corresponding one of said plurality of phase error correction signal generating circuits to provide a proximal clock feedback signal thereto, the proximal end of the other conductor in the given pair being coupled to the corresponding one of said plurality of phase error correction signal generating circuits to provide a distal clock feedback signal thereto, the path lengths of each conductor in the given pair being substantially equal.
Claim 6
Dependent Claim
78 words
The invention of claim 4 wherein said plurality of phase error correction signal generating circuits each includes a phase detector circuit having a first input for receiving the system clock signal, a second input for receiving said proximal clock feedback signal, a third input for receiving said distal clock feedback signal, and an output; and a charge pump having an input coupled to the output of said phase detector circuit and an output coupled to said averaging means.
Claim 7
Dependent Claim
75 words
The invention of claim 4 wherein said averaging means includes a loop filter having an input coupled to said plurality of phase error correction signal generating circuits, and an output; and a delay line having a first input coupled to the output of said loop filter, a second input coupled to said first input terminal, and a plurality of outputs each coupled to a different said one conductor of said plurality of signal conducting members.
Claim 8
Dependent Claim
47 words
The invention of claim 1 wherein said first input terminal, said plurality of clock signal conductor members, said plurality of phase error correction signal generating circuits and said averaging means are all located on a single integrated circuit chip to provide on-chip deskewing of the system clock.
Claim 9
Dependent Claim
60 words
The invention of claim 1 wherein said plurality of phase error correction signal generating circuits and said averaging means are all located on a master clock integrated circuit chip; and wherein said plurality of clock signal conductor members include segments extending from said master clock integrated circuit chip to other integrated circuit chips in order to provide chip-to-chip clock deskewing.
Claim 10
Dependent Claim
187 words
A clock deskewing circuit for substantially deskewing a clock signal, the apparatus comprising: at least a first and a second phase detectors each having a clock terminal for receiving a clock signal and a feedback terminal; at least a first and a second charge pumps coupled to the first and second phase detectors, respectively, for providing at least a first and a second phase error correction signals, respectively; a delay line coupled to at least the first and second charge pumps, the delay line having a clock signal input configured for receiving the clock signal, the delay line having at least a first and a second outputs for coupling a delayed clock signal to at least a first and second loads, respectively, the first output of the delay line coupled to the feedback terminal of the first phase detector, the second output of the delay line coupled to the feedback terminal of the second phase detector for providing to the first and second loads, respectively, a phase delayed clock signal that is based on an average of at least the first and second phase error correction signals.
Claim 11
Dependent Claim
187 words
A clock deskewing circuit for substantially deskewing a clock signal, the apparatus comprising: at least a first and a second phase detectors each having a clock terminal for receiving a clock signal and a feedback terminal; at least a first and a second charge pumps coupled to the first and second phase detectors, respectively, for providing at least a first and a second phase error correction signals, respectively; a delay line coupled to at least the first and second charge pumps, the delay line having a clock signal input configured for receiving the clock signal, the delay line having at least a first and a second outputs for coupling a delayed clock signal to at least a first and second loads, respectively, the first output of the delay line coupled to the feedback terminal of the first phase detector, the second output of the delay line coupled to the feedback terminal of the second phase detector for providing to the first and second loads, respectively, a phase delayed clock signal that is based on an average of at least the first and second phase error correction signals.
Claim 12
Independent Claim
200 words
A method for providing a clock deskewing circuit for substantially synchronizing a clock signal at destination loads with a system clock by averaging delay variations along a plurality of clock distribution paths, the method comprising the steps of: providing a first input terminal for receiving a system clock signal; providing a plurality of clock signal conductor members each having a proximal end and a distal end for providing a phase adjusted clock signal to an associated load device; providing a plurality of phase error correction signal generating circuits each coupled to said first input terminal and to the proximal ends of said plurality of clock signal conductor members for generating a plurality of phase error correction signals each corresponding to the associated load device and each providing a phase correction for any delay associated thereto; and providing averaging means coupled to said plurality of phase error correction signal generator circuits, said first input terminal and said plurality of clock signal conductor members for generating a plurality of substantially identical phase adjusted clock signals each coupled to a different one of said plurality of clock signal conductor members and each incorporating an average of the plurality of phase error correction signals.
Claim 13
Independent Claim
200 words
A method for providing a clock deskewing circuit for substantially synchronizing a clock signal at destination loads with a system clock by averaging delay variations along a plurality of clock distribution paths, the method comprising the steps of: providing a first input terminal for receiving a system clock signal; providing a plurality of clock signal conductor members each having a proximal end and a distal end for providing a phase adjusted clock signal to an associated load device; providing a plurality of phase error correction signal generating circuits each coupled to said first input terminal and to the proximal ends of said plurality of clock signal conductor members for generating a plurality of phase error correction signals each corresponding to the associated load device and each providing a phase correction for any delay associated thereto; and providing averaging means coupled to said plurality of phase error correction signal generator circuits, said first input terminal and said plurality of clock signal conductor members for generating a plurality of substantially identical phase adjusted clock signals each coupled to a different one of said plurality of clock signal conductor members and each incorporating an average of the plurality of phase error correction signals.
Claim 14
Independent Claim
120 words
A method for providing a clock deskewing circuit for substantially synchronizing a clock signal at destination loads with a system clock signal, the method comprising the steps of: receiving the system clock signal on a conductor; generating at least a first and a second phase error correction signal based on phase differences between the system clock signal and at least a first and a second clock signal associated with the destination loads, respectively; generating an average of at least the first and the second phase error correction signals; coupling the average to a delay line for providing at least a first and a second substantially in phase clock signals to at least the first and the second destination loads, respectively.
Claim 15
Independent Claim
120 words
A method for providing a clock deskewing circuit for substantially synchronizing a clock signal at destination loads with a system clock signal, the method comprising the steps of: receiving the system clock signal on a conductor; generating at least a first and a second phase error correction signal based on phase differences between the system clock signal and at least a first and a second clock signal associated with the destination loads, respectively; generating an average of at least the first and the second phase error correction signals; coupling the average to a delay line for providing at least a first and a second substantially in phase clock signals to at least the first and the second destination loads, respectively.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-10-29 | 2000-04-29 | 2000-10-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-10-29 | 2004-04-29 | 2004-10-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-10-29 | 2008-04-29 | 2008-10-29 | $7700.00 | Window Closed / Lapsed |