Application of the phaselock loop to frequency synthesis

Claim 1

A frequency synthesizer for generating a synthesized frequency output signal, said frequency synthesizer having n substantially identical digital module, stages, each of which stages generates one digit of the final frequency number of the synthesized frequency output signal, wherein each digital module stage comprises: a. a phase lock loop receiving only a single input reference frequency signal from a reference signal generator, said phase lock loop comprising: i. a phase comparator receiving said single input reference signal as an input thereto, and generating a phase error signal, ii. a variable frequency oscillator coupled to receive the phase error signal as an input, and generating an output frequency signal for that digital module stage, iii. a digit control circuit means coupled to receive the output frequency signal as an input, said digit control circuit means also receiving a digit control input signal which determines the digit contribution of that digit module stage to the final frequency number of the synthesized frequency output signal, and the output of the digit control circuit means being directed as a second input signal to said phase comparator, which compares it with said reference frequency signal to generate the phase error signal, whereby the digit control input signal determines the output frequency signal for that module stage; b. a digit adder, except the one associated with the first module stage, coupled to receive the output frequency signal from said phase lock loop output and the previous digit module stage as inputs thereto, the digit adder associated with said first stage receiving said phase lock loop output and a reference frequency signal input and producing a digit adder output signal; and c. a digit shifter coupled to receive the digit adder output signal as an input thereto, and producing a shifted digit output signal as an output signal for that digit module stage, which is directed as an input signal to the digit adder of the subsequent digit module stage, or for the last digit module stage forms the synthesized frequency output signal for the frequency synthesizer.