US5008563A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Adjustable clock generator circuit
Assignee: Eastman Kodak Co
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Filing: 1989-09-05
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Granted: 1991-04-16
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Expires: 2009-09-05
Abstract
Abstract A clock generator for producing a pulse that can be adjusted in width and position. The positive edge of an incoming clock signal is slowed by an adjustable rise time inverter with a selected bias voltage until a selected threshold voltage level is met by a Schmitt trigger. The output from the Schmitt trigger is directed through a similar delay circuit to establish the pulse width of the pulse.
Inventors
- 👤 Timothy J. Kenney
- 👤 Lionel J. D'Luna
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 14:13
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/033; H03K5/00; H03K5/13; H03K5/133; H04; H04N; H04N25/00; H04N25/60; H04N25/616; H03K2005/00013; H03K2005/0015; H03K2005/00195
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
244 words
An adjustable clock generator circuit comprising: flip-flop means having a clock input, a clear input, and complementary outputs comprising: first adjustable rise time inverter means having a first input for receiving a phasing input signal, a second input for receiving a first bias voltage for controlling the rise time of its output signal, and an output for providing a first output signal; first trigger means having an input connected to the output of said first adjustable rise time inverter and an output connected to the clock input of said flip-flop means and responsive to said first output signal for providing a pulse transition when said first output signal reaches a trigger voltage; second adjustable rise time inverter means having a first input connected to one output of said flip-flop means and a second input connected to a second bias voltage and an output for providing a second output signal having a rise time controlled by the second bias voltage; second trigger means having an input connected to the output of said second adjustable rise time inverter means and an output connected to the clear input of said flip-flop means for providing a signal transition when said second output signal reaches a trigger voltage, thereby causing signals to appear on the complementary outputs of said flip-flop means with said signals having a pulse position controlled by the level of said first bias voltage and a width controlled by the level of said second bias voltage.
Claim 2
Dependent Claim
244 words
An adjustable clock generator circuit comprising: flip-flop means having a clock input, a clear input, and complementary outputs comprising: first adjustable rise time inverter means having a first input for receiving a phasing input signal, a second input for receiving a first bias voltage for controlling the rise time of its output signal, and an output for providing a first output signal; first trigger means having an input connected to the output of said first adjustable rise time inverter and an output connected to the clock input of said flip-flop means and responsive to said first output signal for providing a pulse transition when said first output signal reaches a trigger voltage; second adjustable rise time inverter means having a first input connected to one output of said flip-flop means and a second input connected to a second bias voltage and an output for providing a second output signal having a rise time controlled by the second bias voltage; second trigger means having an input connected to the output of said second adjustable rise time inverter means and an output connected to the clear input of said flip-flop means for providing a signal transition when said second output signal reaches a trigger voltage, thereby causing signals to appear on the complementary outputs of said flip-flop means with said signals having a pulse position controlled by the level of said first bias voltage and a width controlled by the level of said second bias voltage.
Claim 3
Dependent Claim
34 words
The adjustable clock generator circuit according to claim 1 and further comprising: first inverter means interposed between the first input to said first adjustable rise time inverter means and said received phasing input signal.
Claim 4
Dependent Claim
55 words
The adjustable clock generator circuit according to claim 2 and further comprising: second inverter means interposed between said one complementary output of said flip-flop and the input to said second adjustable rise time inverter; and third inverter means interposed between the output of said second trigger means and the clear input of said flip-flop means.
Claim 5
Dependent Claim
15 words
The adjustable clock generator circuit of claim 1 wherein said flip-flop is a D-type flip-flop.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-04-15 | 1994-10-15 | 1995-04-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-04-15 | 1998-10-15 | 1999-04-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-04-15 | 2002-10-15 | 2003-04-16 | $7700.00 | Window Closed / Lapsed |