US5481573A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Synchronous clock distribution system
Assignee: International Business Machines Corp
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Filing: 1992-06-26
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Granted: 1996-01-02
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Expires: 2012-06-26
Abstract
Abstract A clock signal distribution system for a digital electronic system operating at high clock speed and short cycle times distributes a primary clock signal which is of relatively low frequency through conventional hardware. A high frequency secondary clock signal is generated using a phase locked loop to maintain high accuracy synchronization with the primary clock. Delay means are provided for both the primary and secondary clock signals to provide compensation of propagation time or to provide desired offsets. The phase locked loop arrangements with delays can be cascaded to provide flexibility of both frequency and phase of signals throughout the system, any or all of which may be maintained in synchronism with the primary clock. A dynamic digital transfer function generator is also used within the phase locked loop to achieve particular synchronization functions. The signal distribution system can be used at any or all levels of a network or complex and partitioning of the network or complex may be done based on the articulation of the clock distribution system.
Inventors
- 👤 Lawrence Jacobowitz
- 👤 Daniel Stigliani, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 13:02
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/10; H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/093; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/0635; H04J3/0685; H03L7/07; H04L; H04L7/00; H04L7/02; H04L7/033; H04L7/0337
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
141 words
A clock signal distribution system for an electronic system including a primary clock operating at a predetermined primary frequency, a primary clock signal distribution system having a predetermined bandwidth for distributing said primary clock signal to at least one component of said electronic system, said at least one component including a phase locked loop including an oscillator operating at a secondary frequency outside said predetermined bandwidth and a frequency control means including a dynamic digital transform means for providing a dynamically variable transfer function between a phase detector and said oscillator in said phase locked loop, said phase locked loop maintaining synchronization of said secondary frequency with said primary frequency under control of said dynamic digital transform means, and means for distributing said secondary frequency to at least one element of said system within said component as a secondary clock signal.
Claim 2
Dependent Claim
141 words
A clock signal distribution system for an electronic system including a primary clock operating at a predetermined primary frequency, a primary clock signal distribution system having a predetermined bandwidth for distributing said primary clock signal to at least one component of said electronic system, said at least one component including a phase locked loop including an oscillator operating at a secondary frequency outside said predetermined bandwidth and a frequency control means including a dynamic digital transform means for providing a dynamically variable transfer function between a phase detector and said oscillator in said phase locked loop, said phase locked loop maintaining synchronization of said secondary frequency with said primary frequency under control of said dynamic digital transform means, and means for distributing said secondary frequency to at least one element of said system within said component as a secondary clock signal.
Claim 3
Dependent Claim
31 words
A clock signal distribution system as recited in claim 1, further including means for adjusting the phase of said primary clock signal to produce a primary clock signal having adjusted phase.
Claim 4
Dependent Claim
22 words
A clock signal distribution system as recited in claim 2, further including means for distributing said primary clock signal having adjusted phase.
Claim 5
Dependent Claim
31 words
A clock signal distribution system as recited in claim 1, further including means for adjusting the phase of said secondary clock signal to produce a secondary clock signal having adjusted phase.
Claim 6
Dependent Claim
31 words
A clock signal distribution system as recited in claim 2, further including means for adjusting the phase of said secondary clock signal to produce a secondary clock signal having adjusted phase.
Claim 7
Dependent Claim
69 words
A clock signal distribution system as recited in claim 3, including at least one further component including a further phase locked loop including an oscillator operating at a further secondary frequency, said further phase locked loop maintaining synchronization of said further secondary frequency with a primary frequency, and means for distributing said secondary frequency to at least one element of said system within said at least one further component.
Claim 8
Dependent Claim
29 words
A clock signal distribution system as recited in claim 6, wherein said phase locked loop of said at least one further component is responsive to said primary clock signal.
Claim 9
Dependent Claim
32 words
A clock signal distribution system as recited in claim 6, wherein said phase locked loop of said at least one further component is responsive to said primary clock signal having adjusted phase.
Claim 10
Dependent Claim
67 words
A clock signal distribution system as recited in claim 3, including at least one further component including a further phase locked loop including an oscillator operating at a secondary frequency, said further phase locked loop maintaining synchronization of said secondary frequency with a primary frequency, and means for distributing said secondary frequency to at least one element of said system within said at least one further component.
Claim 11
Dependent Claim
29 words
A clock signal distribution system as recited in claim 9, wherein said phase locked loop of said at least one further component is responsive to said primary clock signal.
Claim 12
Dependent Claim
32 words
A clock signal distribution system as recited in claim 9, wherein said phase locked loop of said at least one further component is responsive to said primary clock signal having adjusted phase.
Claim 13
Dependent Claim
74 words
A clock distribution system as recited in claim 1, wherein said at least one element of said system in said component includes a further phase locked loop including an oscillator operating at a further secondary frequency, said further phase locked loop maintaining synchronization of said further secondary frequency with said secondary frequency, and means for distributing said further secondary frequency to at least one element of said system within said at least one component.
Claim 14
Dependent Claim
31 words
A clock signal distribution system as recited in claim 12, further including means for adjusting the phase of said secondary clock signal to produce a secondary clock signal having adjusted phase.
Claim 15
Dependent Claim
26 words
A clock signal distribution system as recited in claim 12, wherein said further phase locked loop of said element is responsive to said secondary clock signal.
Claim 16
Dependent Claim
29 words
A clock signal distribution system as recited in claim 13, wherein said phase locked loop of said element is responsive to said secondary clock signal having an adjusted phase.
Claim 17
Dependent Claim
20 words
A clock signal distribution system as recited in claim 1, wherein said oscillator includes a surface acoustic wave frequency reference.
Claim 18
Dependent Claim
39 words
A clock signal distribution system as recited in claim 1, wherein said dynamic digital transform means includes a digital controller responsive to at least one of said primary clock signal, said secondary clock signal and an external time reference.
Claim 19
Dependent Claim
19 words
A clock signal distribution system as recited in claim 17, wherein said dynamic digital controller includes a function processor.
References Cited (Backward Citations)
US3812468A
Cited
US3940558A
Cited
US3983501A
Cited
US4185245A
Cited
US4482819A
Cited
US4495614A
Cited
US4694472A
Cited
US4560939A
Cited
US4754164A
Cited
US4686482A
Cited
US4691126A
Cited
US4691176A
Cited
US4847516A
Cited
US5359727A
Cited
US4761567A
Cited
US4755704A
Cited
US4757264A
Cited
US5345449A
Cited
US5125009A
Cited
US5216671A
Cited
US5194828A
Cited
US5291144A
Cited
US5313503A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-01-01 | 1999-07-03 | 2000-01-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-01 | 2003-07-03 | 2004-01-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-01-01 | 2007-07-03 | 2008-01-02 | $7700.00 | Window Closed / Lapsed |