Clock adjustment method and apparatus for synchronous data communications

Claim 2

In a synchronous data communication system comprising a transmitter, a receiver and a common reference clock, said transmitter controlled by a first clock and said receiver controlled by a second clock derived from the common reference clock and having the same nominal frequency as said first clock, apparatus at said transmitter and said receiver for adjusting the phase between said second clock and said first clock, said transmitter apparatus comprising: means for periodically comparing the phase of said first clock with a transmit reference clock derived from the common reference clock; means responsive to said comparing means for periodically generating a phase adjusting signal independent of said second clock indicating a predetermined fixed increment phase adjustment of a fraction of one clock pulse of the common reference clock to be made between said common reference clock and said second clock at said receiver, said predetermined fixed increment phase adjustment being independent of the magnitude of the phase difference between said first clock and said transmit reference clock; means for periodically transmitting said phase adjusting signal to said receiver; and means for adjusting the phase between said first clock and said transmit reference clock by an amount equal to said predetermined fixed increment phase adjustment.

Claim 3

The transmitter apparatus of claim 1 wherein said phase adjusting signal generating means generates a one bit binary signal indicating a positive or a negative predetermined fixed increment phase adjustment for rephasing said second clock.

Claim 4

The transmitter apparatus of claim 1 wherein said phase adjusting signal generating means generates a two bit binary signal indicating a positive, a negative, or no predetermined fixed increment phase adjustment for rephasing said second clock.

Claim 5

In a synchronous data communication system comprising a transmitter, a receiver and a common reference clock, said transmitter controlled by a first clock and a receiver controlled by a second clock derived from said common reference clock having the same nominal frequency as said first clock, a method of adjusting the phase between said second clock and said first clock, at said transmitter: periodically comparing the phase of said first clock with a transmit reference clock derived from the common reference clock; periodically generating in response to said comparing step a phase adjusting signal independent of said second clock indicating a predetermined fixed increment phase adjustment of a fraction of one clock pulse of the common reference clock to be made between said common reference clock and said second clock at said receiver, said predetermined fixed increment phase adjustment being independent of the magnitude of the phase difference between said first clock and said transmit reference clock; periodically transmitting said phase adjusting signal to said receiver; and adjusting the phase between said first clock and said transmit reference clock by an amount equal to said predetermined fixed increment phase adjustment.

Claim 6

In a synchronous data communication system comprising a transmitter, a receiver and a common reference clock, said transmitter controlled by a first clock and a receiver controlled by a second clock derived from said common reference clock having the same nominal frequency as said first clock, a method of adjusting the phase between said second clock and said first clock, at said transmitter: periodically comparing the phase of said first clock with a transmit reference clock derived from the common reference clock; periodically generating in response to said comparing step a phase adjusting signal independent of said second clock indicating a predetermined fixed increment phase adjustment of a fraction of one clock pulse of the common reference clock to be made between said common reference clock and said second clock at said receiver, said predetermined fixed increment phase adjustment being independent of the magnitude of the phase difference between said first clock and said transmit reference clock; periodically transmitting said phase adjusting signal to said receiver; and adjusting the phase between said first clock and said transmit reference clock by an amount equal to said predetermined fixed increment phase adjustment.

Claim 7

The clock phase adjusting method of claim 4 wherein the phase adjusting signal generating step generates a one bit binary phase adjusting signal indicating a positive or a negative predetermined fixed increment phase adjustment.

Claim 8

The clock phase adjusting method of claim 4 wherein the phase adjusting signal generating step generates a two bit binary phase adjusting signal indicating a positive, a negative or no predetermined fixed increment phase adjustment.

Claim 9

In a synchronous data communication system comprising a transmitter, a receiver and a common reference clock, said transmitter controlled by a first clock and said receiver controlled by a second clock derived from the common reference clock and having the same nominal frequency as said first clock, apparatus at said transmitter and said receiver for adjusting the phase between said second clock and said first clock, said transmitter apparatus comprising: means for periodically comparing the phase of said first clock with a transmit reference clock derived from the common reference clock and generating a phase adjusting signal independent of said second clock indicating a predetermined fixed increment phase adjustment of a fraction of one clock pulse of the common reference clock to be made to said transmit reference clock, said predetermined fixed increment phase adjustment being independent of the magnitude of the phase difference between said first clock and said transmit reference clock; means for rephasing said transmit reference clock with said phase adjusting signal; means for periodically transmitting said phase adjusting signal to said receiver; and said receiver apparatus comprising: means for receiving said phase adjusting signal; means for rephasing a receive reference clock with the received phase adjusting signal; and means for generating said second clock of said receiver from said rephased receive reference clock.

Claim 10

In a synchronous data communication system comprising a transmitter, a receiver and a common reference clock, said transmitter controlled by a first clock and said receiver controlled by a second clock derived from the common reference clock and having the same nominal frequency as said first clock, apparatus at said transmitter and said receiver for adjusting the phase between said second clock and said first clock, said transmitter apparatus comprising: means for periodically comparing the phase of said first clock with a transmit reference clock derived from the common reference clock and generating a phase adjusting signal independent of said second clock indicating a predetermined fixed increment phase adjustment of a fraction of one clock pulse of the common reference clock to be made to said transmit reference clock, said predetermined fixed increment phase adjustment being independent of the magnitude of the phase difference between said first clock and said transmit reference clock; means for rephasing said transmit reference clock with said phase adjusting signal; means for periodically transmitting said phase adjusting signal to said receiver; and said receiver apparatus comprising: means for receiving said phase adjusting signal; means for rephasing a receive reference clock with the received phase adjusting signal; and means for generating said second clock of said receiver from said rephased receive reference clock.

Claim 11

In a synchronous data communication system comprising a transmitter, a receiver and a common reference clock, said transmitter controlled by a first clock and a receiver controlled by a second clock derived from the common reference clock and having the same nominal frequency as said first clock, apparatus at said transmitter and said receiver for adjusting the phase between said second clock and said first clock, said transmitter apparatus comprising: means for periodically comparing the phase of said first clock with said common reference clock and generating a phase adjusting signal independent of said second clock indicating a predetermined fixed increment phase adjustment of a fraction of one clock pulse of the common reference clock to be made to said first clock, said predetermined fixed increment phase adjustment being independent of the magnitude of the phase difference between said first clock and said common reference clock; means for rephasing said first clock with said phase adjusting signal; means for periodically transmitting said phase adjusting signal to said receiver; and said receiver apparatus comprising: means for receiving said phase adjusting signal; means for rephasing said second clock relative to said common reference clock using said phase adjusting signal.

Claim 12

In a synchronous data communication system comprising a transmitter, a receiver and a common reference clock, said transmitter controlled by a first clock and a receiver controlled by a second clock derived from the common reference clock and having the same nominal frequency as said first clock, apparatus at said transmitter and said receiver for adjusting the phase between said second clock and said first clock, said transmitter apparatus comprising: means for periodically comparing the phase of said first clock with said common reference clock and generating a phase adjusting signal independent of said second clock indicating a predetermined fixed increment phase adjustment of a fraction of one clock pulse of the common reference clock to be made to said first clock, said predetermined fixed increment phase adjustment being independent of the magnitude of the phase difference between said first clock and said common reference clock; means for rephasing said first clock with said phase adjusting signal; means for periodically transmitting said phase adjusting signal to said receiver; and said receiver apparatus comprising: means for receiving said phase adjusting signal; means for rephasing said second clock relative to said common reference clock using said phase adjusting signal.

Claim 13

The transmitter apparatus of claims 7 or 8 wherein said comparing and phase adjusting signal generating means generates a one bit binary signal indicating a positive or a negative predetermined fixed increment phase adjustment.

Claim 14

The transmitter apparatus of claims 7 or 8 wherein said comparing and phase adjusting signal generating means generates a two bit binary signal indicating a positive, a negative or no predetermined fixed increment phase adjustment.

Claim 17

In a synchronous data communication system comprising a transmitter, a receiver and a common reference clock, said transmitter controlled by a first clock and said receiver controlled by a second clock derived from the common reference clock and having the same nominal frequency as said first clock, a method of adjusting the phase between said second clock and said first clock, at said transmitter: periodically comparing the phase of said first clock with a transmit reference clock derived from the common reference clock and generating a phase adjusting signal independent of said second clock indicating a predetermined fixed increment phase adjustment of a fraction of one clock pulse of the common reference clock to be made to said transmit reference clock, said predetermined fixed increment phase adjustment being independent of the magnitude of the phase difference between said first clock and said transmit reference clock; rephasing said transmit reference clock with said phase adjusting signal; transmitting said phase adjusting signal to said receiver; and at said receiver: receiving said phase adjusting signal; rephasing a receive reference clock derived from the common reference clock with the received phase adjusting signal; and generating said second clock at said receiver from said rephased receive reference clock.

Claim 18

In a synchronous data communication system comprising a transmitter, a receiver and a common reference clock, said transmitter controlled by a first clock and said receiver controlled by a second clock derived from the common reference clock and having the same nominal frequency as said first clock, a method of adjusting the phase between said second clock and said first clock, at said transmitter: periodically comparing the phase of said first clock with a transmit reference clock derived from the common reference clock and generating a phase adjusting signal independent of said second clock indicating a predetermined fixed increment phase adjustment of a fraction of one clock pulse of the common reference clock to be made to said transmit reference clock, said predetermined fixed increment phase adjustment being independent of the magnitude of the phase difference between said first clock and said transmit reference clock; rephasing said transmit reference clock with said phase adjusting signal; transmitting said phase adjusting signal to said receiver; and at said receiver: receiving said phase adjusting signal; rephasing a receive reference clock derived from the common reference clock with the received phase adjusting signal; and generating said second clock at said receiver from said rephased receive reference clock.

Claim 19

In a synchronous data communication system comprising a transmitter, a receiver and a common reference clock, said transmitter controlled by a first clock and a receiver controlled by a second clock derived from the common reference clock and having the same nominal frequency as said first clock, a method of adjusting the phase between said second clock and said first clock, at said transmitter: periodically comparing the phase of said first clock with said common reference clock and generating a phase adjusting signal independent of said second clock indicating a predetermined fixed increment phase adjustment of a fraction of one clock pulse of the common reference clock to be made to said first clock, said predetermined fixed increment phase adjustment being independent of the magnitude of the phase difference between said first clock and said common reference clock; rephasing said first clock with said phase adjusting signal; periodically transmitting said phase adjusting signal to said receiver; and at said receiver: receiving said phase adjusting signal; rephasing said second clock relative to said common reference clock using said phase adjusting signal.

Claim 20

In a synchronous data communication system comprising a transmitter, a receiver and a common reference clock, said transmitter controlled by a first clock and a receiver controlled by a second clock derived from the common reference clock and having the same nominal frequency as said first clock, a method of adjusting the phase between said second clock and said first clock, at said transmitter: periodically comparing the phase of said first clock with said common reference clock and generating a phase adjusting signal independent of said second clock indicating a predetermined fixed increment phase adjustment of a fraction of one clock pulse of the common reference clock to be made to said first clock, said predetermined fixed increment phase adjustment being independent of the magnitude of the phase difference between said first clock and said common reference clock; rephasing said first clock with said phase adjusting signal; periodically transmitting said phase adjusting signal to said receiver; and at said receiver: receiving said phase adjusting signal; rephasing said second clock relative to said common reference clock using said phase adjusting signal.

Claim 21

The clock phase adjusting method of claims 13 or 14 wherein the periodically comparing and phase adjusting signal generating step generates a one bit binary phase adjusting signal indicating a positive or a negative predetermined fixed increment phase adjustment.

Claim 22

The clock phase adjusting method of claims 13 or 14 wherein the periodically comparing and phase adjusting signal generating step generates a two bit binary phase adjusting signal indicating a positive, a negative or no predetermined fixed increment phase adjustment.

Claim 23

The clock phase adjusting method of claims 13 or 14 including the step of generating a common reference clock locally at said transmitter and said receiver from a system clock signal.

Claim 24

The clock phase adjusting method of claims 13 or 14 further including the step of at said transmitter: multiplexing said phase adjusting signal into a data stream for transmission to said receiver; and at said receiver: demultiplexing said phase adjusting signal from the received data stream.