US4189622A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data communication system and bit-timing circuit
Assignee: Raytheon Co
•
Filing: 1977-11-01
•
Granted: 1980-02-19
•
Expires: 1997-11-01
Abstract
Abstract A digital timing system and method is disclosed for improving the bit-error-rate performance of digital communications systems, such as satellite communications links which experience deep fades caused by ionospheric scintillation with resultant loss of synchronization for multibit time durations. The present invention prevents timing loss and bit-shift under such ionospheric conditions, and is also applicable to land lines, computer communications links and any other communication channels vulnerable to timing loss and resultant data bit-shift caused by noise, extraneous transitions or transmission line anamolies. A novel bit-timing circuit is described which analyzes incoming phase-shifted digital data transitions to select a "best-fit" clock from a plurality of discrete clocks of like frequency but displaced in phase for clocking the data. The discrete clocks are derived directly from a highly stable crystal oscillator source. Incoming data transitions are converted to pulses multiplexed in time to divide the data bit periods into a plurality of incremental time intervals, each time interval being associated with a data accumulator and one of said discrete clocks for counting data transitions over a predetermined number of bits. The contents of the accumulators are monitored to determine whether the data therein is valid or invalid, with a preponderance of data in any one accumulator being indicative of valid data. Valid data is clocked out by the "best-fit" clock while an invalid data indication inhibits the shifting of clock phase until valid data is again received.
Inventors
- 👤 James J. Foshee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 18:43
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H04L7/0337; H04L7/0338
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
221 words
A circuit for synchronizing an incoming digital data bit stream clocked by a PRESENT CLOCK signal with a BEST-FIT clock signal, comprising: dividing means for dividing each bit period into a plurality of increments, each increment being representative of a different transition phase shift; transition means operatively connected to said dividing means for counting the number of data transitions which occur during each of said bit increments for a predetermined number of bits; logic means operatively connected to said transition means for generating a digital code representative of the increment containing the greatest transition count; clock generation means for generating a plurality of phased clock signals of like frequency but different phase, each clock signal being associated with one of said bit increments; clock signal selection means for comparing said PRESENT CLOCK signal with said digital code for selecting said BEST-FIT clock signal from one of said phased clock signals for synchronizing said data with said BEST-FIT clock signal such that said BEST-FIT clock signal become the PRESENT CLOCK signal for the next comparison; and data validating means responsive to said transition means for inhibiting said clock signal selection means so as to prevent said PRESENT CLOCK from shifting to become said adjacent phased clock signal when more than one of said bit increments contains transitions counted by said transition means.
Claim 2
Dependent Claim
221 words
A circuit for synchronizing an incoming digital data bit stream clocked by a PRESENT CLOCK signal with a BEST-FIT clock signal, comprising: dividing means for dividing each bit period into a plurality of increments, each increment being representative of a different transition phase shift; transition means operatively connected to said dividing means for counting the number of data transitions which occur during each of said bit increments for a predetermined number of bits; logic means operatively connected to said transition means for generating a digital code representative of the increment containing the greatest transition count; clock generation means for generating a plurality of phased clock signals of like frequency but different phase, each clock signal being associated with one of said bit increments; clock signal selection means for comparing said PRESENT CLOCK signal with said digital code for selecting said BEST-FIT clock signal from one of said phased clock signals for synchronizing said data with said BEST-FIT clock signal such that said BEST-FIT clock signal become the PRESENT CLOCK signal for the next comparison; and data validating means responsive to said transition means for inhibiting said clock signal selection means so as to prevent said PRESENT CLOCK from shifting to become said adjacent phased clock signal when more than one of said bit increments contains transitions counted by said transition means.
Claim 3
Dependent Claim
149 words
A circuit for synchronizing phase shifted data bits when a clock signal comprising: means for dividing each of said data bits into a plurality of increments; transition means for counting the number of data transitions which occur during said increments for a predetermined number of bits; means for generating a signal indicative of the particular increment containing the most transitions counted over said predetermined number of bits; means for generating a plurality of phased clock signals of like frequency but different phase, each of said phased clock signals being associated with one of said increments; means for selecting one of said phased clock signals in response to said generated signal; means for utilizing said selected phased clock signal to synchronize said data; and data validation means for inhibiting said means for selecting one of said phased clock signals when more than one of said bit increments contains data transitions.
Claim 4
Dependent Claim
149 words
A circuit for synchronizing phase shifted data bits when a clock signal comprising: means for dividing each of said data bits into a plurality of increments; transition means for counting the number of data transitions which occur during said increments for a predetermined number of bits; means for generating a signal indicative of the particular increment containing the most transitions counted over said predetermined number of bits; means for generating a plurality of phased clock signals of like frequency but different phase, each of said phased clock signals being associated with one of said increments; means for selecting one of said phased clock signals in response to said generated signal; means for utilizing said selected phased clock signal to synchronize said data; and data validation means for inhibiting said means for selecting one of said phased clock signals when more than one of said bit increments contains data transitions.
Claim 5
Dependent Claim
229 words
A bit-timing circuit for deriving a clock signal synchronous with the data transitions of a stream of digital data bits during intervals of phase shift of said data bits, comprising: means for generating N phased clock signals, of like frequency but displaced in phase, one from the other, by 360°/N wherein N is an integer greater than ONE; transition conditioning means for converting said data transitions into pulses; means for dividing each bit period into N portions during certain of which portions said pulses occur; N accumulator means coupled to the output of said dividing means for counting the transitions occurring during said N portions of said bit period, over a predetermined multi-bit time interval, each of said N portions being associated with one of said accumulators; means for analyzing the contents of said N accumulators for determining which accumulator contains the greatest count, and for generating a signal representative of said determination; clock selection means responsive to the signal generated by said analyzing means for selecting one of said N phased clock signals for clocking said data such that said selected clock signal is in phase with the portion of said bit period during which most of said transitions occur; and data validation circuit means for inhibiting said clock selection means for switching from said input clock signal when more than one N accumulator means contains data transitions.
Claim 6
Dependent Claim
229 words
A bit-timing circuit for deriving a clock signal synchronous with the data transitions of a stream of digital data bits during intervals of phase shift of said data bits, comprising: means for generating N phased clock signals, of like frequency but displaced in phase, one from the other, by 360°/N wherein N is an integer greater than ONE; transition conditioning means for converting said data transitions into pulses; means for dividing each bit period into N portions during certain of which portions said pulses occur; N accumulator means coupled to the output of said dividing means for counting the transitions occurring during said N portions of said bit period, over a predetermined multi-bit time interval, each of said N portions being associated with one of said accumulators; means for analyzing the contents of said N accumulators for determining which accumulator contains the greatest count, and for generating a signal representative of said determination; clock selection means responsive to the signal generated by said analyzing means for selecting one of said N phased clock signals for clocking said data such that said selected clock signal is in phase with the portion of said bit period during which most of said transitions occur; and data validation circuit means for inhibiting said clock selection means for switching from said input clock signal when more than one N accumulator means contains data transitions.
Claim 7
Dependent Claim
42 words
A bit-timing circuit in accordance with claim 3 wherein said data validation circuit means further comprises means responsive to the number of accumulator transitions so as to inhibit said clock selection means when the number of accumulator transitions exceeds a predetermined amount.
Claim 8
Dependent Claim
161 words
A circuit for synchronizing phase shifted data transitions with a clock comprising: means for dividing each of the data bit periods during which said transitions occur into a plurality of increments; accumulator means operatively responsive to said means for dividing for counting the number of transitions which occur during each of said increments for a predetermined number of bits; means operatively responsive to said accumulator means for generating a digital code indicative of the bit increment containing the most transitions counted over said predetermined number of bits; means for generating a plurality of phased clocks of like frequency but different phase, each of said phased clock being associated with one of said increments; means for selecting one of said phased clocks in accordance with said digital code for synchronizing said data; and data validation means responsive to said generated digital code for inhibiting said means for selecting one of said phase clocks when transitions are counted in more than one increment.
Claim 9
Dependent Claim
161 words
A circuit for synchronizing phase shifted data transitions with a clock comprising: means for dividing each of the data bit periods during which said transitions occur into a plurality of increments; accumulator means operatively responsive to said means for dividing for counting the number of transitions which occur during each of said increments for a predetermined number of bits; means operatively responsive to said accumulator means for generating a digital code indicative of the bit increment containing the most transitions counted over said predetermined number of bits; means for generating a plurality of phased clocks of like frequency but different phase, each of said phased clock being associated with one of said increments; means for selecting one of said phased clocks in accordance with said digital code for synchronizing said data; and data validation means responsive to said generated digital code for inhibiting said means for selecting one of said phase clocks when transitions are counted in more than one increment.
Claim 10
Dependent Claim
52 words
A circuit in accordance with claim 5 and further comprising: means for detecting the transition count in increments other than the increment containing the highest transition count and for providing an output to said data validation means when the count exceeds a predetermined amount, so as to inhibit said clock selecting means.
Claim 11
Independent Claim
135 words
A method of synchronizing phase shifted data bits with a clock comprising the steps of: dividing each of said data bits into a plurality of increments; counting the number of data transitions which occur during said increments for a predetermined number of bits; generating a selection signal indicative of the particular increment containing the most transitions counted over said predetermined number of bits; generating a plurality of phased clocks of like frequency but different phase, each of said phased clocks being associated with one of said increments; selecting one of said phased clocks in response to said selection signal; utilizing said selected phased clock to synchronize said data; and determining whether more than one increment contains data transitions; inhibiting the selection of said phased clocks when data transitions are counted in more than one increment.
Claim 12
Independent Claim
135 words
A method of synchronizing phase shifted data bits with a clock comprising the steps of: dividing each of said data bits into a plurality of increments; counting the number of data transitions which occur during said increments for a predetermined number of bits; generating a selection signal indicative of the particular increment containing the most transitions counted over said predetermined number of bits; generating a plurality of phased clocks of like frequency but different phase, each of said phased clocks being associated with one of said increments; selecting one of said phased clocks in response to said selection signal; utilizing said selected phased clock to synchronize said data; and determining whether more than one increment contains data transitions; inhibiting the selection of said phased clocks when data transitions are counted in more than one increment.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-02-18 | 1983-08-20 | 1984-02-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-02-18 | 1987-08-20 | 1988-02-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-02-18 | 1991-08-20 | 1992-02-19 | $7700.00 | Window Closed / Lapsed |