High frequency character receiver

Claim 2

For use in a data receiver having a delay line for receiving character start and data pulses and providing at least three output ports each of which supplies a different delay signal sample of said start and data pulses, a source for supplying clock pulse signals, a shift register for receiving start and data pulses serially via said delay line ports and supplying said received pulses in parallel to a utilization means, the improvement comprising Selection means including a plurality of subcircuits responsive to a receipt of delay signal samples from said output ports and to supplied clock pulse signals for selecting delayed start and data pulses on any one of said output ports for synchronized operation with said clock pulse signals in the transmission of said start and data pulses from said delay line ports to said shift register.

Claim 3

The invention of claim 1 wherein each of the subcircuits comprises bistable elements for storing successive start and data pulses from said output ports, and logic elements responsive to supplied clock pulse signals cooperating with ones of delay signal samples stored in said bistable elements for selecting a synchronized one of said output ports for transmission of said signal samples from said selected port to said shift register.

Claim 4

The invention of claim 2 wherein said bistable elements comprise a group of flip-flops for storing a present sample of delay signal samples from said output ports and other flip-flops for storing delay signal samples previously stored in said first mentioned flip-flops and said logic elements comprise a group of selection flip-flops responsive to stored signals in said first mentioned and other flip-flops for selecting any one of said output ports for synchronized operation with said clock pulse signals in the transmission of said start and delay pulses from said delay line ports to said shift register.

Claim 5

A receiver operated by clock signals of a prescribed frequency for providing phase-synchronization between said clock signals and character pulses arriving at the same frequency comprising, means having a plurality of output ports and being responsive to an arrival of a pulse on an input port for consecutively generating on said output ports a plurality of partially coincident signals of a prescribed duration and including means for delaying a generation of succesive ones of said signals by a prescribed time interval less than said duration, means actuated by said clock signals for sampling states of each of said output ports, and means responsive to prescribed sequences of samples of said output port states signfiying one of said output ports synchronized with said clock signals for selecting said last-mentioned one of said ports for synchronized character pulse reception.

Claim 6

A receiver operated by clock signals of a prescribed frequency for providing phase-synchronization between said clock signals and character pulses arriving at the same frequency comprising, means having a plurality of output ports and being responsive to an arrival of a pulse on an input port for consecutively generating on said output ports a plurality of partially coincident signals of a prescribed duration and including means for delaying a generation of succesive ones of said signals by a prescribed time interval less than said duration, means actuated by said clock signals for sampling states of each of said output ports, and means responsive to prescribed sequences of samples of said output port states signfiying one of said output ports synchronized with said clock signals for selecting said last-mentioned one of said ports for synchronized character pulse reception.

Claim 7

A receiver comprising a source of clock signals and a register for providing phase synchronization between character pulses arriving at a prescribed frequency and clock signals occurring at the same frequency comprising, means having an input port and a plurality of output ports and being responsive to an application of a character pulse on said input port for consecutively generating signals of a prescribed duration on successive ones of said output ports, and wherein said generating means includes means for delaying an appearance of said signals on consecutive ones of said output ports by a prescribed time interval less than said prescribed duration, means connected to ones of said output ports and being actuated by said clock signals for storing most recent samples of said signals, means responsive to prescribed states of said storing means signifying a receipt of a character start pulse for selecting for synchronized character pulse reception a preferred one of said output ports priorly containing thereon one of said signals the duration of which is approximately centered with respect to one of said clock signals, and means enabled by said selecting means for steering samples of succeeding signals obtained from said preferred one of said output ports from said storing means to said register.

Claim 8

A receiver comprising a source of clock signals and a register for providing phase synchronization between character pulses arriving at a prescribed frequency and clock signals occurring at the same frequency comprising, means having an input port and a plurality of output ports and being responsive to an application of a character pulse on said input port for consecutively generating signals of a prescribed duration on successive ones of said output ports, and wherein said generating means includes means for delaying an appearance of said signals on consecutive ones of said output ports by a prescribed time interval less than said prescribed duration, means connected to ones of said output ports and being actuated by said clock signals for storing most recent samples of said signals, means responsive to prescribed states of said storing means signifying a receipt of a character start pulse for selecting for synchronized character pulse reception a preferred one of said output ports priorly containing thereon one of said signals the duration of which is approximately centered with respect to one of said clock signals, and means enabled by said selecting means for steering samples of succeeding signals obtained from said preferred one of said output ports from said storing means to said register.

Claim 9

The invention of claim 5 wherein said delaying means further comprises a delay line having said input port and plural output ports.

Claim 10

The invention of claim 5 wherein said storing means comprises a plurality of first storage elements each of which is connected to an individual one of said output ports for storing samples of said signals, and a plurality of second storage elements each of which is connected to an individual one of said first storage elements for storing samples of states of said first storage elements.

Claim 11

The invention of claim 7 wherein each of said first and second storage elements comprises a plurality of bistable devices and logic gate means controlled by said clock signals for storing in the respective bistable devices samples of said output ports and said first storage elements.

Claim 12

The invention of claim 5 wherein said selecting means comprises decoding means for detecting said prescribed states of said storing means signifying arrival of said start pulse, and means operated by said decoding means for enabling said steering means to establish a communication path between said preferred one of said ports and said register and including said storing means.

Claim 13

A receiver for receiving character start and data pulses of a prescribed frequency and including a source of clock signals of said prescribed frequency and a shift register comprising, means having an input port and at least three output ports and being responsive to an application of a character pulse of prescribed duration on said input port for consecutively generating a signal of said prescribed duration on successive ones of said output ports, wherein said generating means includes, means intermediate each pair of consecutive ones of said output ports for delaying appearances of said signal therebetween by a predetermined time interval equal to said prescribed duration divided by the number of said output ports, means comprising a plurality of storage elements each of which is connected to an individual one of said output ports and being actuated by said clock signals for storing samples of states of said output ports, decoding means responsive to prescribed sequences of said samples and signifying a signal sample on one of said output ports synchronized with a said clock signal with said clock signal centered in occurrence proximate to a midpoint in the duration of said signal sample, means operated by said decoding means for selecting one of said storage elements monitoring said one of said output ports, and means enabled by said selecting means for steering succeeding samples from said one of said storage elements to said shift register.

Claim 14

A receiver for receiving character start and data pulses of a prescribed frequency and including a source of clock signals of said prescribed frequency and a shift register comprising, means having an input port and at least three output ports and being responsive to an application of a character pulse of prescribed duration on said input port for consecutively generating a signal of said prescribed duration on successive ones of said output ports, wherein said generating means includes, means intermediate each pair of consecutive ones of said output ports for delaying appearances of said signal therebetween by a predetermined time interval equal to said prescribed duration divided by the number of said output ports, means comprising a plurality of storage elements each of which is connected to an individual one of said output ports and being actuated by said clock signals for storing samples of states of said output ports, decoding means responsive to prescribed sequences of said samples and signifying a signal sample on one of said output ports synchronized with a said clock signal with said clock signal centered in occurrence proximate to a midpoint in the duration of said signal sample, means operated by said decoding means for selecting one of said storage elements monitoring said one of said output ports, and means enabled by said selecting means for steering succeeding samples from said one of said storage elements to said shift register.

Claim 15

The invention of claim 10 wherein said generating means further comprises a delay line including a plurality of serially-connected delay elements individual ones of which are connected intermediate consecutive ones of said output ports and being effective for providing a time delay equal to said predetermined interval of said signal therebetween.

Claim 16

The invention of claim 11 wherein said storage elements further comprise a plurality of first flip-flops each of which is connected to an individual one of said output ports and operable under control of said clock signals for storing said samples of said states of said output ports, a plurality of second flip-flops, and a plurality of gates connecting individual ones of said first flip-flops to individual ones of said second flip-flops for transferring stored samples from said first flip-flops for storage in said second flip-flops.

Claim 17

The invention of claim 12 wherein said decoding means comprises a plurality of decoding gates having connections to ones of said first and second flip-flops, individual ones of said decoding gates being effective for detecting individual ones of said prescribed sequences of said samples, and wherein said selecting means comprises a plurality of selection flip-flops individual ones of which are operated by individual ones of said decoding gates in response to a detection of predetermined ones of said prescribed sequences.

Claim 18

The invention of claim 13 wherein said selecting means further comprises a plurality of holding gates connecting individual ones of said decoding gates to individual ones of said selection flip-Flops, and wherein each of said holding gates has a connection from an output of one of said selection flip-flops for maintaining an operated state of said one of said selection flip-flops.

Claim 19

The invention of claim 14 wherein said steering means comprises a plurality of steering gates each of which is connected to individual ones of said selection flip-flops and being operable under control of said last-mentioned flip-flops and clock signals for steering samples from selectable ones of said second flip-flops to said register.