Patent CN1154582C successfully refreshed from Google Patents.
US3648248A
Expired / Lapsed
US
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Apparatus including sampling and quantizing means for discriminating received digital signals
Assignee: Thales SA
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Filing: 1970-06-08
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Granted: 1972-03-07
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Expires: 1990-06-08
Abstract
Abstract A device for processing digital pulse code modulated signals comprises means for sampling and quantizing the signal at a frequency which is a multiple of that at which the digits are transmitted. These samples are stored and summed after each sampling operation. The result of the summing is fed to reference threshold devices to generate the requisite parameters for the control of the receiver, by means of logic circuits.
Inventors
- 👤 Pierre Deman
- 👤 Jean Pierre Gouyet
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 14:55
CPC Classifications
H; H01; H01B; H01B17/00; H01B17/14; H01B17/145; H04; H04L; H04L25/00; H04L25/02; H04L25/06; H04L25/068; H04L5/00; H04L5/02; H04L5/04
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
182 words
A device for processing digital signals having a plurality of nominal levels, comprising: a clock having a phase control input, a first output for delivering pulses at a first frequency equal to the frequency F of digital transmission and a second output for delivering pulses at the frequency mF, where m is an integer greater than 1; a series circuit comprising an input filter, means coupled to said second output for sampling said digital signals at said frequency mF and coding the amplitude of each sample by a number also expressed in digital form, means for storing the m samples resulting from the coding of the last obtained successive m samples, and means, having an output, for summing said m samples; a transition detector having an input coupled to said output of said summing means, and an output coupled to said phase control input; and a digit discriminator having a first input coupled to said output of said summing means, a second input coupled to said first output of said clock, and p outputs, p being the number of said nominal levels.
Claim 2
Independent Claim
182 words
A device for processing digital signals having a plurality of nominal levels, comprising: a clock having a phase control input, a first output for delivering pulses at a first frequency equal to the frequency F of digital transmission and a second output for delivering pulses at the frequency mF, where m is an integer greater than 1; a series circuit comprising an input filter, means coupled to said second output for sampling said digital signals at said frequency mF and coding the amplitude of each sample by a number also expressed in digital form, means for storing the m samples resulting from the coding of the last obtained successive m samples, and means, having an output, for summing said m samples; a transition detector having an input coupled to said output of said summing means, and an output coupled to said phase control input; and a digit discriminator having a first input coupled to said output of said summing means, a second input coupled to said first output of said clock, and p outputs, p being the number of said nominal levels.
Claim 3
Dependent Claim
155 words
A device as claimed in claim 1, wherein: a gain control circuit, having a gain control input, and a circuit, haviNg a AC control input, for adjusting the DC component of said signals, are inserted in series between said input filter and said sampling means; said device also comprises an incremental corrector having a first input coupled to said first output of said clock, a second input coupled to said output of said summing means, p other inputs respectively coupled to said p outputs of said digit discriminator, a first output coupled to said gain control input, and a second output coupled to said DC control input; said coding means comprise a binary coding device having 2n levels, n being a given positive integer; and said storing means are a shift register including m sets of n parallel-connected binary elements, the stepping of said shift register being controlled by said pulses at said frequency mF.
Claim 4
Dependent Claim
107 words
A device as claimed in claim 2, wherein p 2 and wherein said transition detector comprises means for delivering an output pulse when the value of any one of the sums delivered by said summing means is equal to a predetermined level; said digit discriminator comprising means, controlled by said pulses at said frequency F, for comparing said sums to said predetermined level, said predetermined level delimiting two successive ranges of values respectively associated with said outputs of said digit discriminator, said digit discriminator further comprising means for delivering a pulse at a given output when a sum is comprised in the range of values associated therewith.
Claim 5
Dependent Claim
103 words
A device as claimed in claim 3, wherein said incremental corrector has further inputs coupled to said outputs of said digit discriminator and wherein, said two successive ranges of values being respectively associated with two predetermined intermediate thresholds respectively comprised in said two ranges, said incremental corrector comprises means for comparing each of said sums with said predetermined level and said two intermediate thresholds and for delivering to said gain control input and to said DC control input control signals as a function of the results of the comparisons effected by said comparing means and of the signals delivered by said digit discriminator.
Claim 6
Dependent Claim
69 words
A device as claimed in claim 1, wherein said summing means include weighting means for respectively weighting the values of said last obtained, successive m samples according to their position number in the series of said m successive samples and wherein the sums delivered by said summing means are the correspondly weighted sums, and wherein said input filter is a low-pass filter constituted by a resistor and a capacitor.
References Cited (Backward Citations)
US3249878A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-03-07 | 1975-09-06 | 1976-03-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-03-07 | 1979-09-06 | 1980-03-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-03-07 | 1983-09-06 | 1984-03-07 | $7700.00 | Window Closed / Lapsed |