US3873773A — Forward bit count integrity detection and correct…

Claim 1

Independent Claim 155 words

In an asynchronous multiplex-demultiplex system in which there are provided means for transmitting a control code for each channel of the system, and for each transmitted control code, there are provided one or more associated sequence time slots in the transmitted data stream, the improvement comprising: means for inserting into each of said associated sequence time slots, at least one bit of a known N bit sequence respectively associated with K transmitted control codes; and means for receiving said control codes and said N bit sequences and including means for locally generating one of K known N bit sequences in the same sequence as that inserted into said sequence time slots in response to successive detections of said received control codes, and means for comparing each detected control code''a associated N bit sequence with that generated in response to the detection of said control code and providing an output misalignment indication when said sequences differ.

Claim 2

Dependent Claim 155 words

In an asynchronous multiplex-demultiplex system in which there are provided means for transmitting a control code for each channel of the system, and for each transmitted control code, there are provided one or more associated sequence time slots in the transmitted data stream, the improvement comprising: means for inserting into each of said associated sequence time slots, at least one bit of a known N bit sequence respectively associated with K transmitted control codes; and means for receiving said control codes and said N bit sequences and including means for locally generating one of K known N bit sequences in the same sequence as that inserted into said sequence time slots in response to successive detections of said received control codes, and means for comparing each detected control code''a associated N bit sequence with that generated in response to the detection of said control code and providing an output misalignment indication when said sequences differ.

Claim 3

Dependent Claim 32 words

The system as defined in claim 1 wherein said control codes are controlled by the relation existing between the channel sample rate and the input data rate on a per channel basis.

Claim 4

Dependent Claim 29 words

The system as defined in claim 2 in which the channel sample rate can be faster than, slower than, or interchangeably faster and slower than the input data rate.

Claim 5

Dependent Claim 43 words

The system as defined in claim 1 in which means are provided for utilizing said control codes to control the phase of the transmitted sequence, the phase of the transmitted sequence providing an absolute relative count on the type of control code transmitted.

Claim 6

Dependent Claim 56 words

The system as defined in claim 4 in which means are provided at the receiver means for ascertaining the phase relation between the received sequence and the locally generated sequence, with such phase information revealing whether the received control codEs are the same as those transmitted, and means for interpreting any misalignment of the control codes.

Claim 7

Dependent Claim 64 words

The system as defined in claim 5 in which means are provided at the receiver for determining the phase misalignment, with the direction of the misalignment indicating the type of error made, and the magnitude of the phase misalignment indicating the number of errors made, and means for enabling channel data bits to be added or deleted as necessary to restore bit count integrity.

Claim 8

Dependent Claim 156 words

In an asynchronous multiplex-demultiplex system in which there are provided means for transmitting a control code, and for each transmitted control code, there is provided an associated predetermined sequence time slot in the transmitted data stream, the improvement comprising: means for inserting into each of said associated sequence time slots, one of N known sequences respectively associated with K transmitted control codes, means for controlling the phase of the known sequence by means of the control code being transmitted, and means for receiving said control codes and said sequences and including means for locally generating one of N known sequences in an exact same sequence as that inserted into said sequence time slots in response to successive detections of said K received control codes, and means for comparing each detected control code''s associated sequence with that generated in response to the detection of said control code and providing an output misalignment indication when said sequences differ.

Claim 9

Dependent Claim 156 words

In an asynchronous multiplex-demultiplex system in which there are provided means for transmitting a control code, and for each transmitted control code, there is provided an associated predetermined sequence time slot in the transmitted data stream, the improvement comprising: means for inserting into each of said associated sequence time slots, one of N known sequences respectively associated with K transmitted control codes, means for controlling the phase of the known sequence by means of the control code being transmitted, and means for receiving said control codes and said sequences and including means for locally generating one of N known sequences in an exact same sequence as that inserted into said sequence time slots in response to successive detections of said K received control codes, and means for comparing each detected control code''s associated sequence with that generated in response to the detection of said control code and providing an output misalignment indication when said sequences differ.

Claim 10

Dependent Claim 33 words

The system as defined in claim 7 in which said control codes are controlled by the relation existing between the channel sample rate and the input data rate on a per channel basis.

Claim 11

Dependent Claim 29 words

The system as defined in claim 8 in which the channel sample rate can be faster than, slower than, or interchangeably faster and slower than the input data rate.

Claim 12

Dependent Claim 55 words

The system as defined in claim 7 in which means are provided at the receiver means for ascertaining the phase relation between the received sequence and the locally generated sequence, with such phase information revealing whether the received control codes are the same as those transmitted, and means for ascertaining misalignment of the control codes.

Claim 13

Dependent Claim 59 words

The system as defined in claim 10 in which said means provided at the receiver for determining the misalignment ascertain from the direction of any misalignment, the type of error made, and from the magnitude of any misalignment, the number of errors made, and means for adding or deleting channel data bits as necessary to restore bit count integrity.

Claim 14

Dependent Claim 197 words

In an asynchronous digital multiplex-demultiplex system having a plurality of transmission channels, with each channel including means for transmitting a control code and, for each transmitted control code, one or more associated predetermined sequence time slots in the transmitted data stream, the improvement on a per channel basis comprising: first bit pattern sequence generator means at the transmitter terminal for sequentially inserting into said transmitted data stream during the sequence time slots, K known bit patterns, with the bit patterns being respectively associated with 1 to K transmitted control codes; and the receiving terminal for each transmission channel including: actuatable second bit pattern sequence generator means for sequentially generating an exact same sequence of bit patterns as that sequentially inserted by said first generator means; means for sequentially actuating said second generator means in response to sequentially detected control codes received at the receiving terminal; and means for comparing each bit pattern generated by said second generating means in response to a detected said control code, with the received bit pattern associated with the detected control code providing an output misalignment indication when a said received bit pattern is not aligned with the associated generated bit pattern.

Claim 15

Dependent Claim 197 words

In an asynchronous digital multiplex-demultiplex system having a plurality of transmission channels, with each channel including means for transmitting a control code and, for each transmitted control code, one or more associated predetermined sequence time slots in the transmitted data stream, the improvement on a per channel basis comprising: first bit pattern sequence generator means at the transmitter terminal for sequentially inserting into said transmitted data stream during the sequence time slots, K known bit patterns, with the bit patterns being respectively associated with 1 to K transmitted control codes; and the receiving terminal for each transmission channel including: actuatable second bit pattern sequence generator means for sequentially generating an exact same sequence of bit patterns as that sequentially inserted by said first generator means; means for sequentially actuating said second generator means in response to sequentially detected control codes received at the receiving terminal; and means for comparing each bit pattern generated by said second generating means in response to a detected said control code, with the received bit pattern associated with the detected control code providing an output misalignment indication when a said received bit pattern is not aligned with the associated generated bit pattern.

Claim 16

Dependent Claim 48 words

In a system As set forth in claim 12 including error ascertaining means responsive to a said output misalignment indication for ascertaining whether the misalignment was caused by a bit error in one of said received bit patterns, or an error in detection of a said control code.

Claim 17

Dependent Claim 88 words

In a system as set forth in claim 12 wherein said error ascertaining means includes counting means that, when activated, counts N received pulse codes and then provides an output search command signal, and alarm means for activating said counting means for the duration of a said output misalignment indication so that an output search command is provided only when a misalignment continues for a count of N received stuff codes, indicative that the misalignment was caused by an error in detection of at least one stuff code.

Claim 18

Dependent Claim 40 words

In a system as set forth in claim 14 wherein said alarm means includes a bistable control means having a normal first state, and a second state for activating said counting means for the duration of an output misalignment indication.

Claim 19

Dependent Claim 54 words

In a system as set forth in claim 15 wherein said counting means includes an N bit digital counter and gating means enabled so long as said alarm bistable control means is in its second state, for actuating said counter by one count each time a stuff code is detected at said receiving terminal.

Claim 20

Dependent Claim 80 words

In a system as set forth in claim 13 wherein said receiving terminal includes a multibit register means for receiving each said received bit pattern transmitted from said transmitting terminal, said comparing means being connected to other bit of said sequence, said second bit pattern generator means sequentially providing means and said second generator means for comparing each said received bit pattern with the bit pattern generated by said second generator means to ascertain whether said bit patterns are aligned.

Claim 21

Dependent Claim 70 words

In a system as set forth in claim 17 wherein the first said transmitted bit pattern includes at least one bit of a known multibit sequence with the successively transmitted bit pattern each including at least one sequentially providing an exact same sequence of said bit patterns so that if each transmitted stuff code is received then the respective received bit patterns and generated bit patterns should be in alignment.

Claim 22

Dependent Claim 41 words

In a system as set forth in claim 13 including control code correction means for modifying said data stream to compensate for stuff code errors, spill code errors, or no action code errors in detecting said code at said receiving terminal.

Claim 23

Dependent Claim 65 words

In a system as set forth in claim 19 wherein said control code correction means includes: means for storing the received bit pattern resulting in a said misalignment indication; and search means for sequentially actuating said second generator means so that its sequentially generated bit patterns are compared one at a time with the stored said received bit pattern until said misalignment indication is terminated.

Claim 24

Dependent Claim 36 words

In a system as set forth in claim 20 including sequence generator counting means for counting the number of times said second generator means is actuated by said search means before said misalignment indication is terminated.

Claim 25

Dependent Claim 33 words

In a system as set forth in claim 21 including correction control means for varying the data stream by a predetermined number of bits for each count of said sequence generator counting means.

Claim 26

Dependent Claim 39 words

In a system as set forth in claim 22 wherein said correction control means includes means for adding at least one data bit to said data stream for each of certain specific counts of said sequence generator counting means.

Claim 27

Dependent Claim 39 words

In a system as set forth in claim 22 wherein said correction control means includes means for deleting at least one data bit from said data stream for each of certain other counts of said sequence generator counting means.

Claim 28

Dependent Claim 76 words

In a system as set forth in claim 22 wherein said sequence generator means is an N bit up-down counter for counting upward by one count for each actuation by said search means and wherein said correction control means includes decoding means for respectively providing a count down command or a count up command in dependence upon whether the count of said up-down counter is less than or is equal to or greater than N/2 counts.

Claim 29

Dependent Claim 243 words

In an asynchronous digital multiplex-demultiplex system having means at the transmitter terminal for inserting stuff codes into the transmitted data stream for each transmission channel so that a stuff time slot is provided in the data stream and associated with a transmitted stuff code, the improvement in a said system for preserving bit integrity between the data bits from an asynchronous data source applied to the transmitting terminal and the demultiplexed data bits at the receiving terminal, and comprising for each transmission channel: first bit sequence generator means at the transmitting terminal responsive to each transmitted stuff code for inserting a bit pattern of a known N bit digital sequence into the associated stuff bit time slot, said generator means sequentially inserting said bit patterns for successively transmitted stuff codes so that each said bit pattern is associated with one of N said transmitted stuff codes; and the receiving terminal includes: means for detecting said transmitted stuff codes; second bit sequence generator means for sequentially generating in response to successive said stuff code detections an exact same sequence of bit patterns as that sequentially inserted by said first generator means; means for receiving the inserted said bit pattern associated with each detected stuff code; and, means for comparing the bit pattern generated in response to a detection of a stuff code with the bit pattern associated with the detected stuff code and providing an output indication when said bit patterns do not compare.

Claim 30

Dependent Claim 243 words

In an asynchronous digital multiplex-demultiplex system having means at the transmitter terminal for inserting stuff codes into the transmitted data stream for each transmission channel so that a stuff time slot is provided in the data stream and associated with a transmitted stuff code, the improvement in a said system for preserving bit integrity between the data bits from an asynchronous data source applied to the transmitting terminal and the demultiplexed data bits at the receiving terminal, and comprising for each transmission channel: first bit sequence generator means at the transmitting terminal responsive to each transmitted stuff code for inserting a bit pattern of a known N bit digital sequence into the associated stuff bit time slot, said generator means sequentially inserting said bit patterns for successively transmitted stuff codes so that each said bit pattern is associated with one of N said transmitted stuff codes; and the receiving terminal includes: means for detecting said transmitted stuff codes; second bit sequence generator means for sequentially generating in response to successive said stuff code detections an exact same sequence of bit patterns as that sequentially inserted by said first generator means; means for receiving the inserted said bit pattern associated with each detected stuff code; and, means for comparing the bit pattern generated in response to a detection of a stuff code with the bit pattern associated with the detected stuff code and providing an output indication when said bit patterns do not compare.

Claim 31

Dependent Claim 39 words

In a system as set forth in claim 26 wherein said receiving terminal includes error determining means controlled by a said output indication for ascertaining the number of errors made in detecting stuff codes resulting in said output indication.

Claim 32

Dependent Claim 50 words

In a system as set forth in claim 27 wherein said receiving terminal includes bit corrector means for varying the number of data bits in the data stream at said receiving terminal in dependence upon the number of said errors in detecting stuff codes so as to preserve bit integrity.

Claim 33

Dependent Claim 48 words

In a system as set forth in claim 28 wherein said error determining means includes circuit means for providing an indication as to whether a said error in detecting a stuff code was a failure to detect a stuff code or a false detection of a stuff code.

Claim 34

Dependent Claim 43 words

In a system as set forth in claim 29 wherein said circuit means includes a bit pattern sequence counter means for providing a count indication, the decimal value of which is indicative of the type of said error in detecting a stuff code.

Claim 35

Independent Claim 159 words

A method of preserving bit integrity in an asynchronous multiplexer-demultiplexer system employing pulse stuff/spill operations and comprising the steps of: inserting a control code in the transmitted data stream so that one or more sequence time slots are associated with the control code, for each transmitted control code, inserting at least one bit of a known digital sequence in the associated sequence time slot, with the phase of the sequence being controllable, in response to each control code detected at the receiving terminal of said system, generating at least one bit of an exact same sequence as that inserted into the transmitted data stream, the phase of the transmitted sequence being controlled by the control code to be transmitted and the phase of the receiver local sequence generator being controlled by the received control code, and varying the number of data bits in the received data stream when the sequences are not aligned so as to preserve bit integrity.

Claim 36

Independent Claim 159 words

A method of preserving bit integrity in an asynchronous multiplexer-demultiplexer system employing pulse stuff/spill operations and comprising the steps of: inserting a control code in the transmitted data stream so that one or more sequence time slots are associated with the control code, for each transmitted control code, inserting at least one bit of a known digital sequence in the associated sequence time slot, with the phase of the sequence being controllable, in response to each control code detected at the receiving terminal of said system, generating at least one bit of an exact same sequence as that inserted into the transmitted data stream, the phase of the transmitted sequence being controlled by the control code to be transmitted and the phase of the receiver local sequence generator being controlled by the received control code, and varying the number of data bits in the received data stream when the sequences are not aligned so as to preserve bit integrity.

Claim 37

Dependent Claim 38 words

A method as set forth in claim 31 wherein the number of data bits to be varied in the received data stream is dependent upon the magnitude of the misalignment between the received sequence and the local sequence.

Claim 38

Dependent Claim 64 words

A method as set forth in claim 32 wherein a given number of data bits are added to the received data stream or a given number of data bits are deleted from the received data stream in dependence upon whether the number of times in a given number of operations that said sequences do not compare is above or below a given count number.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1978-03-24	1978-09-23	1979-03-25	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1982-03-24	1982-09-23	1983-03-25	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1986-03-24	1986-09-23	1987-03-25	$7700.00	Window Closed / Lapsed

Forward bit count integrity detection and correction technique for asynchronous systems

Abstract

Inventors

Bibliographic Details

Claims Analysis

References Cited (Backward Citations)

USPTO Annuity & Maintenance Windows

Assigned Categories & Tags

Assign Category Tag