Clock phasing circuit

Claim 2

A clock phasing circuit for aligning serial digital data which is transmitted by a first clock running at a particular frequency with a second clock running at essentially the same frequency as the first clock but having a time varying phase relationship, said circuit comprising a plurality of bit storage elements for sequentially storing the data bits transmitted by said first clock, a plurality of first logic gates with each of said gates having an input connected to receive the output of a respective one of said bit storage elements, a second logic gate having its inputs connected to the outputs of each of said first logic gates, and means connected to said second clock for controlling the operation of said first logic gates so that said data bits are transferred through said second logic gate in the proper sequence whereby said data is reformed in phase shifted relationship.

Claim 3

A clock phasing circuit according to claim 1 including means for detecting a synchronizing bit which precedes said data bits in the data transmitted by said first clock, and means connected between said synchronizing bit detecting means and said means for controlling the operation of said first logic gates for initiating the transfer of data bits through said second logic gate in a predetermined manner.

Claim 4

A clock phasing circuit according to claim 1 including an output bit storage element connected to the output of said second logic gate, and means controlling the transfer of said data through said output bit storage element at transfer times different from those times when said data bits are transferred through said second logic gate.

Claim 5

A clock phasing circuit according to claim 3 wherein said second clock is arranged to produce a pair of pulse trains 180° out of phase with each other, one of said pulse trains of the second clock being utilized by said means for controlling the transfer for data through said output bit storage element and the other of said pulse trains of the second clock being utilized by said means for controlling the operation of said first logic gates.

Claim 6

A clock phasing circuit according to claim 1 including means for switching said first clock to said means for controlling the operation of said first logic gates in the event of failure of said second clock.

Claim 7

A clock phasing circuit for aligning serial digital data which is transmitted by a first clock running at a particular frequency with a second clock running at essentially the same frequency as the first clock but having a time varying phase relationship, said circuit comprising first and second bit holding elements, means for alternately clocking said data bit by bit into said first and second bit holding elements upon successive pulses from said first clock, a first logic gate connected to the output of said first bit holding element and a second logic gate connected to the output of said second bit holding element, means controlled by said second clock for alternately enabling said first and second logic gates, and means connected to the outputs of said logic gates for combining the signals therefrom so that the data is reformed in alignment with said second clock.

Claim 8

A clock phasing circuit for aligning serial digital data which is transmitted by a first clock running at a particular frequency with a second clock running at essentially the same frequency as the first clock but having a time varying phase relationship, said circuit comprising first and second bit holding elements, means for alternately clocking said data bit by bit into said first and second bit holding elements upon successive pulses from said first clock, a first logic gate connected to the output of said first bit holding element and a second logic gate connected to the output of said second bit holding element, means controlled by said second clock for alternately enabling said first and second logic gates, and means connected to the outputs of said logic gates for combining the signals therefrom so that the data is reformed in alignment with said second clock.

Claim 9

A clock phasing circuit according to claim 6 including means for switching said first clock to said means for alternately enabling said first and second logic gates in the event of failure of said second clock.

Claim 10

A clock phasing circuit according to claim 6 wherein said means for combining the signals from said logic gates includes a third bit holding element, said second clock being arranged to produce a pair of pulse trains 180° out of phase with each other, one of said pulse trains of the second clock being connected to said means for alternately enabling said first and second logic gates and the other of said pulse trains of the second clock being connected to said third bit holding element.

Claim 11

A clock phasing circuit according to claim 6 wherein said means for clocking said data into said bit holding elements comprises a flip flop with its clock input connected to receive successive pulses from said first clock, and a pair of control gates connected to the outputs of said flip flop, said control gates being connected so as to alternately clock said first and second bit holding elements.

Claim 12

A clock phasing circuit according to claim 9 including means for detecting a synchronizing bit which precedes the data bits in the data transmitted by said first clock, and means connected between said synchronizing bit detecting means and said flip flop and between said synchronizing bit detecting means and said means for enabling said first and second logic gates for initiating the transfer of data bits into said bit holding elements and through said logic gates in a predetermined manner.

Claim 13

A clock phasing circuit for aligning serial digital data which is transmitted by a first clock running at a particular frequency with a second clock running at essentially the same frequency as the first clock but having a time varying phase relationship, said circuit comprising first and second bit holding elements, means for alternately clocking said data bit by bit into said first and second bit holding elements upon successive pulses from said first clock, said last named means being operative to maintain said data bits in said bit holding elements for time periods substantially longer than that of the original data bit periods, a first logic gate connected to the output of said first bit holding element and a second logic gate connected to the output of said second bit holding element, means controlled by said second clock for alternately enabling said first and second logic gates at the frequency of said second clock, a third logic gate connected to the outputs of said first and second logic gates, data transfer means connected to the output of said third logic gate to receive the combined data bit signals therefrom, and means for shifting said data bit signals through said data transfer means at said second clock frequency and 180° out of phase with the second clock signal provided by said means for alternately enabling said first and second logic gates whereby said data is reformed in alignment with said second clock.

Claim 14

A clock phasing circuit for aligning serial digital data which is transmitted by a first clock running at a particular frequency with a second clock running at essentially the same frequency as the first clock but having a time varying phase relationship, said circuit comprising first and second bit holding elements, means for alternately clocking said data bit by bit into said first and second bit holding elements upon successive pulses from said first clock, said last named means being operative to maintain said data bits in said bit holding elements for time periods substantially longer than that of the original data bit periods, a first logic gate connected to the output of said first bit holding element and a second logic gate connected to the output of said second bit holding element, means controlled by said second clock for alternately enabling said first and second logic gates at the frequency of said second clock, a third logic gate connected to the outputs of said first and second logic gates, data transfer means connected to the output of said third logic gate to receive the combined data bit signals therefrom, and means for shifting said data bit signals through said data transfer means at said second clock frequency and 180° out of phase with the second clock signal provided by said means for alternately enabling said first and second logic gates whereby said data is reformed in alignment with said second clock.