US3593160A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Clock-synchronizing circuits
Assignee: Fujitsu Services Ltd
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Filing: 1968-11-21
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Granted: 1971-07-13
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Expires: 1988-11-21
Abstract
Abstract A system for the generation of clock signals in a data processing apparatus is disclosed, in which the clock signals are developed from a source of higher frequency pulses. The clock signals are applied to an apparatus in which data signals are represented in nonreturn-to-zero (NRZ) manner, and the clock signals are synchronized to the occurrence of changes in data item representation. It is recognized that the synchronization of the signals may vary and, in particular that there is a condition of spurious synchronization in which the clock signals may occur 180* out of phase with data changes. The system proposed is arranged to recognize both variations in synchronism and the spurious synchronism condition and to correct the relative timing between clock and data change signals to bring the system into true synchronism by modifying the application of the higher frequency pulses to a clock signal generating countdown arrangement.
Inventors
- 👤 John Richard Moore
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 18:31
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13; H03K5/01; H03K5/04; H03K5/05; H04; H04L; H04L7/00; H04L7/02; H04L7/033
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
196 words
A clock-synchronizing circuit including a source of first pulses at a substantially constant repetition frequency; a countdown circuit; a first gating circuit connected between said source of first pulses and said countdown circuit, the countdown circuit being operable to produce timing signals in response to successively applied predetermined numbers of pulses with the timing signals occurring at time intervals of predetermined duration; said first gating circuit arranged to pass only alternate ones of said first pulses from said source of first pulses to said countdown circuit; a data signal source producing a signal having significant transitions each representing a change in data significance; marking pulse-generating means responsive to said data signal to generate a marking pulse for each change in data significance, the marking pulses being timed to occur between said alternate ones of said first pulses and a second gating circuit responsive to said marking pulses and to said timing signals and operable in response to the occurrence of a first pair of successive marking signals within one of said timing intervals to apply the second marking pulse of said first pair to said countdown circuit to shorten a following one of said time intervals.
Claim 2
Dependent Claim
196 words
A clock-synchronizing circuit including a source of first pulses at a substantially constant repetition frequency; a countdown circuit; a first gating circuit connected between said source of first pulses and said countdown circuit, the countdown circuit being operable to produce timing signals in response to successively applied predetermined numbers of pulses with the timing signals occurring at time intervals of predetermined duration; said first gating circuit arranged to pass only alternate ones of said first pulses from said source of first pulses to said countdown circuit; a data signal source producing a signal having significant transitions each representing a change in data significance; marking pulse-generating means responsive to said data signal to generate a marking pulse for each change in data significance, the marking pulses being timed to occur between said alternate ones of said first pulses and a second gating circuit responsive to said marking pulses and to said timing signals and operable in response to the occurrence of a first pair of successive marking signals within one of said timing intervals to apply the second marking pulse of said first pair to said countdown circuit to shorten a following one of said time intervals.
Claim 3
Dependent Claim
55 words
A system as claimed in claim 1 in which said data signal source produces a data signal having two levels representing respectively data items of opposite binary significance, the data signal changing from one to the other level only if the binary significance of a data item differs from that of the immediately preceding item.
Claim 4
Dependent Claim
39 words
A system as claimed in claim 1 in which said marking generator means includes a device switchable between two stable states, said device being responsive to changes in data signal levels to switch from one state to the other.
Claim 5
Dependent Claim
79 words
A system as claimed in claim 3 in which said marking pulse generator also includes a third gating circuit having first and second AND gates, each of which is responsive to said device in one stable state, respectively, with each AND gate also being responsive to those of said first pulses not passed by said first gating circuit such that said third gating circuit passes one of those first pulses for every change of level of said data signal.
Claim 6
Dependent Claim
142 words
A system as claimed in claim 1 including means responsive to the output of said countdown circuit to produce an indicating pulse once during each of said timing intervals, said second gating circuit including a bistable element which may be conditioned in a first or second stable state, the first input of the bistable element being responsive to the output of said marking pulse generator with the second input thereto being responsive to said indicating pulse, and a third AND gate one input of which is responsive to the output of the marking pulse generator and the other input being responsive to said bistable element conditioned in a first state such that upon a pair of marking pulses being produced between two indicating signals, the second marking pulse of said pair is passed by said third AND gate to said countdown circuit.
Claim 7
Dependent Claim
68 words
A system as claimed in claim 1 in which the countdown circuit includes a binary counting chain having a plurality of cascaded binary stages to produce a clock pulse train consisting of a substantially symmetrical square waveform having two levels in response to the application to the countdown circuit of a sEries of regularly occurring pulses; and means for deriving said timing signals from the clock pulse train.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-07-12 | 1975-01-11 | 1975-07-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-07-12 | 1979-01-11 | 1979-07-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-07-12 | 1983-01-11 | 1983-07-13 | $7700.00 | Window Closed / Lapsed |