Line variation compensation system for synchronized pcm digital switching

Claim 2

A line synchronizer system for use with a digital PCM communication switching network receiving thereto a frequency synchronized digital PCM carrier pulse data train to be switched, said PCM pulse train arranged in a cyclic time frame format of repeating frame periods and having sporadically occurring phase misalignments due to line variation phenomena, said line synchronizer system comprising a digital phase detector subsystem repeatedly detecting said phase misalignment, said phase detector subsystem including first time delay means recieving said P.C.M. data train for compensating for said phase misalignments of less than one full pulse period and further including first logic means connected to said first time delay means for providing first and second output signals of opposite polarity corresponding to phase misalignments of at least one full pulse period in positive and negative directions, respectively, a frame detector subsystem including means for generating a first cyclic timing pattern, detector means for receiving said P.C.M. pulse train and detecting misalignments of said P.C.M. pulse train with said reference timing pattern during each of a plurality of repeating time periods, said detector means providing an error signal in response to a predetermined number of said phase misalignments, first counter means including means for advancing the state thereof when either of said first output signal from said first logic means or said error signal occurs and means for regressing the state of said first counter means when said second output signal from said first logic means occurs, and an elastic buffer register store subsystem including second time delay means being connected to said first counter means and connected for receiving said P.C.M. pulse train, said second time delay means selectively imparting to said PCM pulse train a predetermined number of time delay periods equal to an integral multiple of the frame period of said PCM pulse train, said predetermined number of time delay periods being correspondingly increased with said count state advances of and correspondingly decreased with said count state regressions of said first counter means, respectively, first gating means connecting said PCM pulses to said second time delay means, and second gating means connected to said second time delay means for activating the transfer of said PCM pulses within said second time delay means prior to a subsequent operation of said first gating means.

Claim 3

A line synchronizer system as claimed in claim 1 wherein said first time delay means of said phase detector subsystem receives said PCM pulse train and includes a plurality of access output data taps for providing therefrom said PCM pulse train having preselected magnitudes of time delays, respectively, only one of said access output data taps being utilized at any given time, and said first logic means includes detector means for detecting said phase misalignments in said positive and negative directions, second counter means for counting cumulatively said positive and negative directional phase misalignments which occur within a framing bIt period for said PCM pulse train, respectively, means for changing said access output data taps in a first direction corresponding to said counted positive directional phase misalignments, respectively, and in a second direction corresponding to said counted negative directional phase misalignments, respectively, for varying said preselected magnitude of time delay, said first output signal from said first logic means occurring for a preselected number of cumulative changes of said access output data taps in said first direction and said negative output signal thereof occurring for a corresponding preselected number of cumulative changes of said access output data taps in said second direction.

Claim 4

A line synchronizer system as claimed in claim 2 wherein said first time delay means is a three bit cell shift register having four access output data taps arranged with respect to said bit cells to provide 0*, 90*, 180* and 270* phase delays at said four access output data taps, respectively, out of 360* phase delay corresponding to one full pulse period.

Claim 5

A line synchronizer system as claimed in claim 1 wherein said PCM pulse train is arranged in a cyclic time frame format having repeating frame periods and said comparing means of said frame detector subsystem is active within a preselected number of pulse periods within each of said frame periods.

Claim 6

A line synchronizer system as claimed in claim 4 wherein said preselected number of pulse periods are adjacent and continuously occurring pulse periods and constitute a frame search window.

Claim 7

A line synchronizer system as claimed in claim 4 wherein said second time delay means of said elastic buffer register store subsystem comprises a shift register having bit cells providing cumulative time delays and corresponding in number to said preselected number of pulse periods within each of said frame period for which said comparing means of said frame detector subsystem is active, each of said bit cells providing a time delay of substantially one pulse period, said first gating means comprises a plurality of write circuits associated correspondingly with the inputs of said bit cells for writing said PCM pulses into said bit cells, respectively, and said second gating means includes a plurality of shift circuits associated correspondingly with the inputs of said bit cells for transferring said PCM pulses from a preceding bit cell prior to the occurrence of the next succeeding PCM pulse and to said write circuit of the associated bit cell with the occurrence of said next succeeding PCM pulse, and means for selecting a first bit cell of said preselected number of bit cells in accordance with the cumulative count of said first counter means of said frame detector subsystem.

Claim 8

A line synchronizer system for use with a communication swtiching network useful for switching a synchronized digital PCM pulse data train arranged in a cyclic time frame format of repeating frame periods and having sporadically occurring bi-directional phase misalignments due to line variation phenomena, said line synchronizer system comprising: a digital phase detector subsystem including first logic means receiving said P.C M. data train for detecting said phase misalignments which occur in positive and negative directions, said first logic means providing first and second output signals corresponding to positive and negative phase misalignments of at least one pulse period, respectively, and third output signals corresponding to detected phase misalignments of less than one pulse period, first time delay means receiving said PCM pulse train and said third output signals and delaying said PCM pulse train by preselected magnitudes of time corresponding to said third output signals, a frame detector subsystem including means for generating a reference timing pattern, detector means for receiving said PCM pulse train and detecting misalignments of said PCM pulse train with said reference timing pattern during each of a plurality of repeating time periods, said detector means providing an error signal in response to a predetermined number of said phase misalignments, and an elastic buffer register store subsystem including a plurality of cumulatively arranged time delay devices, each thereof having a pair of input terminals for receiving individual PCM pulses and an output terminal for transmitting said PCM pulses with a time delay of substantially one pulse period, a corresponding plurality of first gating circuits connected to one of said input terminals of associated ones of said time delay devices, respectively, for successively writing said individual PCM pulses into said associated time delay devices, a corresponding plurality of second gating circuits connected to the other of said input terminals of said time delay devices, respectively, said second gating circuits further being connected to an immediately preceding one of said time delay devices for transferring said PCM pulses therefrom prior to the writing of the next succeeding PCM pulse and further transferring said PCM pulses to said associated time delay devices with the occurrence of said next succeeding PCM pulse, and second logic means for selecting a first time delay device of said plurality of time delay devices, said second logic means receiving thereto said first and second output signals from said digital phase detector subsystem and said error signals from said frame detector subsystem to enable said selection.

Claim 9

A line synchronizer system for use with a communication swtiching network useful for switching a synchronized digital PCM pulse data train arranged in a cyclic time frame format of repeating frame periods and having sporadically occurring bi-directional phase misalignments due to line variation phenomena, said line synchronizer system comprising: a digital phase detector subsystem including first logic means receiving said P.C M. data train for detecting said phase misalignments which occur in positive and negative directions, said first logic means providing first and second output signals corresponding to positive and negative phase misalignments of at least one pulse period, respectively, and third output signals corresponding to detected phase misalignments of less than one pulse period, first time delay means receiving said PCM pulse train and said third output signals and delaying said PCM pulse train by preselected magnitudes of time corresponding to said third output signals, a frame detector subsystem including means for generating a reference timing pattern, detector means for receiving said PCM pulse train and detecting misalignments of said PCM pulse train with said reference timing pattern during each of a plurality of repeating time periods, said detector means providing an error signal in response to a predetermined number of said phase misalignments, and an elastic buffer register store subsystem including a plurality of cumulatively arranged time delay devices, each thereof having a pair of input terminals for receiving individual PCM pulses and an output terminal for transmitting said PCM pulses with a time delay of substantially one pulse period, a corresponding plurality of first gating circuits connected to one of said input terminals of associated ones of said time delay devices, respectively, for successively writing said individual PCM pulses into said associated time delay devices, a corresponding plurality of second gating circuits connected to the other of said input terminals of said time delay devices, respectively, said second gating circuits further being connected to an immediately preceding one of said time delay devices for transferring said PCM pulses therefrom prior to the writing of the next succeeding PCM pulse and further transferring said PCM pulses to said associated time delay devices with the occurrence of said next succeeding PCM pulse, and second logic means for selecting a first time delay device of said plurality of time delay devices, said second logic means receiving thereto said first and second output signals from said digital phase detector subsystem and said error signals from said frame detector subsystem to enable said selection.

Claim 10

A line synchronizer system as claimed in claim 7 wherein said predetermined number of time delay periods is equal to an integral multiple of the frame period of said PCM pulse train, and said detector means is active within a preselected number of consecutively occurring pulse periods within each of said frame periods.

Claim 11

A line synchronizer system as claimed in claim 8 wherein said frame detector subsystem includes first counter means including means for advancing the count thereof with the occurrence of either one of said first output signals from said phase detector subsystem or said error signals and for regressing the count thereof with the occurrence of said second output signals from said pase detector subsystem, respectively, and said second logic means selects said first time delay device of said elastic buffer register subsystem in accordance with the cumulative count of said first counter means of said frame detector subsystem.

Claim 12

A time synchronizer system as claimed in claim 8 wherein said digital phase detector subsystem further includes second reference timing means for providing cyclically occurring first and second detector pulse trains having the trailing edges of the individual pulses of said first detector pulse train and the leading edges of the individual pulses of said second detector pulse train time aligned with the occurrences of the leading and trailing edges of the individual pulses of said PCM pulse train, respectively, second means for detecting phase shifts of said individual PCM pulses in said positive and said negative directions through detecting simultaneous occurrences of said individual PCM pulses with the occurrences of the pulses of said second and said first pulse trains, respectively, decoder means for decreasing and increasing said preselected magnitudes of time delay with each of said positive and negative directional phase shifts, respectively, which occur within said preselected number of consecutively occurring pulse periods within each of said frame periods whereby phase misalignments of less than one full pulse period are compensated for.

Claim 13

A line synchronizer system as claimed in claim 8 wherein said detector means is active within eight consecutively occurring pulse periods within each of said repeating frame periods and said detector means provides said error signal in response to two occurrences of phase misalignments in the first four consecutively occurring frame periods, at least one Occurrence of phase misalignments out of eight consecutively occurring frame periods, and at least three occurrences of phase misalignments in any four consecutively occurring frame periods out of eight frame periods.