Programmable high speed digital phase locked loop

Claim 2

A digital phase locked loop comprising: a phase detector receiving input digital data at a first input, a low pass filter connected to an output of the phase detector, and a digitally controlled oscillator connected to an output of said low pass filter, an output of the digitally controlled oscillator being connected to a second input of the phase detector to form a loop with said digitally controlled oscillator generating a clock output and said phase detector comparing said clock output with input digital data; a delay string connected to said digitally controlled oscillator; and speed monitoring means responsive to said delay string for determining variations in circuit speed of the digital phase locked loop due to at least one of manufacturing and environmental conditions, said speed monitoring means generating a first control digital word used by said low pass filter to adjust dynamic characteristics of the low pass filter.

Claim 3

The digital phase locked loop recited in claim 1 further comprising bandwidth regulator means connected to receive said first control digital word from said speed monitoring means for generating a second control digital word, said low pass filter using said second control digital to set a threshold to determine when to make a phase adjustment in said digitally controlled oscillator output.

Claim 4

The digital phase locked loop recited in claim 2 further comprising: a second, slave digitally controlled oscillator for generating a system clock; programmable phase shifter means responsive to said low pass filter and said first control digital word from said speed monitoring means for controlling the frequency of said second, slave digitally controlled oscillator; and retiming latch means for receiving input digital data and controlled by said system clock for generating retimed digital data output.

Claim 5

The digital phase locked loop recited in claim 1 wherein said digitally controlled oscillator comprises: a crystal oscillator for generating a precision frequency reference signal, said delay string being connected to said crystal oscillator and outputting a plurality of precision frequency reference signals having different delays; clock phase select multiplexer means connected to receive said plurality of precision frequency reference signals from said delay string; and decoder means responsive to said low pass filter for generating a control signal for said clock phase select multiplexer means for selecting one of said plurality of precision frequency reference signals as said output of said digitally controlled oscillator.

Claim 6

The digital phase locked loop recited in claim 4 wherein said speed monitoring means comprises: delay string snapshot means connected to said delay string for periodically sampling a state of said delay string; and delay tree size generator means connected to said delay string snapshot means for determining a last non-redundant delay element in said delay string and for generating said first control digital word.

Claim 7

The digital phase locked loop recited in claim 3 wherein said digitally controlled oscillator comprises: a crystal oscillator for generating a precision frequency reference signal, said delay string being connected to said crystal oscillator and outputting a plurality of precision frequency reference signals having different delays; clock phase select multiplexer means connected to receive said plurality of precision frequency reference signals from said delay string; and decoder means responsive to said low pass filter for generating a control signal for said clock phase select multiplexer means for selecting one of said plurality of precision frequency reference signals as said output of said digitally controlled oscillator.

Claim 8

The digital phase locked loop recited in claim 6 wherein said speed monitoring means comprises: delay string snapshot means connected to said delay string for periodically sampling a state of said delay string; and delay tree size generator means connected to said delay string snapshot means for determining a last non-redundant delay element in said delay string and for generating said first control digital word.

Claim 9

The digital phase locked loop recited in claim 7 wherein said programmable phase shifter means comprises: phase constant generator means for combining said first control digital word with a phase offset factor to generate a control signal representing a number of delay elements required to achieve a desired phase offset for a sampling clock; and phase offset generator means responsive to said control signal from said phase constant generator means for computing a delay string position of the sampling clock by adding the number of delay elements required to a delay string position as indicated by an output of said low pass filter.

Claim 10

The digital phase locked loop recited in claim 8 wherein said second, slave digitally controlled oscillator comprises: second clock phase selector multiplexer means connected to receive said plurality of precision frequency reference signals from said delay string; and second decoder means responsive to said phase offset generator means for generating a control signal for said second clock phase select multiplexer means for selecting one of said plurality of precision frequency reference signals as said sampling clock.

Claim 11

The digital phase locked loop recited in claim 8 wherein said low pass filter comprises: first up/down counter means for incrementing a count in response to a lag condition output from said phase detector and for decrementing a count in response to a lead condition output from said phase detector; magnitude comparator means for monitoring a count accumulated by said first up/down counter means and for resetting said first up/down counter means when a count of said first up/down counter means is equal to either a lagging threshold value or a leading threshold value; and second up/down counter means responsive to said magnitude comparator means for incrementing a count when said first up/down counter is reset by said magnitude comparator upon said lagging threshold value being equaled by the count of said first up/down counter means and for decrementing a count when said first up/down counter is reset by said magnitude comparator upon said leading threshold value being equaled by the count of said first up/down counter means, the count accumulated by said second up/down counter means being supplied to said phase offset generator means as said delay string position.

Claim 12

The digital phase locked loop recited in claim 10 wherein said second up/down counter means is preconditioned by said speed monitoring means so that when said second up/down counter means needs to decrement below a value of zero, it checks the value of said first control digital word and uses that value as a new value, and when said second up/down counter means is incrementing, it checks said first digital control word to determine whether its current count is greater than said first digital control word and, when said current count is greater than said first digital control word, said second up/down counter is reset to zero.

Claim 13

The digital phase locked loop recited in claim 10 wherein said phase detector comprises: phase detector circuit means responsive to said clock output from said digitally controlled oscillator and said input digital data for providing an output signal indicative of a phase difference between said clock output from said digitally controlled oscillator and said input digital data; 180° clock circuit means responsive to a delayed version of said clock output from said digitally controlled oscillator and said input digital data for providing an output signal indicative of a phase difference between said delayed version of said clock output from said digitally controlled oscillator and said input digital data, said delayed version of said clock output being output by said digitally controlled oscillator and being a clock output having a delay; and lag/lead generator means responsive to said phase detector circuit means and said 180° clock circuit means for producing a respective lag and lead condition output and for forcing a clock leading data condition when a 180° out of phase lock condition is detected.