US4988960A
Expired / Lapsed
US
⏱️ 0.0 years remaining
FM demodulation device and FM modulation device employing a CMOS signal delay device
Assignee: Yamaha Corp
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Filing: 1989-12-08
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Granted: 1991-01-29
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Expires: 2009-12-08
Abstract
Abstract A signal delay device comprises a CMOS gate circuit having an input terminal to which a binary input signal to be delayed is applied, an output terminal from which a delayed signal is derived and power voltage supply terminals to which operation power voltages are applied. The delay time of the CMOS gate circuit depends upon voltage applied to it and, utilizing this phenomenon, voltage control means is provided in a power supplying path for the CMOS gate circuit for controlling voltage applied to the CMOS gate circuit. The signal delay device using the CMOS gate circuit is applied to various circuits including a FM modulator or FM demodulator. The signal delay device will assure undistorted signals.
Inventors
- 👤 Norio Tomisawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 01:53
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/0805; H03C; H03C3/00; H03C3/10; H03C3/24; H03C3/245; H03D; H03D3/00; H03D3/02; H03D3/04; H03D3/18; H03D3/20; H03K; H03K5/00; H03K5/13; H03K5/133; H03L7/099; H03L7/0995; H03K2005/00013; H03K2005/00078; H03K2005/00097; H03K2005/00104; H03K2005/00143; H03K2005/0015; H03K2005/00195
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
350 words
A pulse count detection circuit comprising: (a) phase locked-loop means for producing a control signal including: a ring oscillator circuit including a first CMOS gate circuit having an input terminal to which a binary input signal to be delayed is applied and an output terminal, a first power voltage control means for controlling an operation power voltage applied to the first CMOS gate circuit thereby to control an amount of delay of the first CMOS gate circuit and a feedback path for connecting said output of said first CMOS gate circuit back to said input of said first CMOS gate circuit; reference signal generation means for generating a reference signal of constant frequency; comparison means for comparing the phase of said reference signal to the phase of the output of said first CMOS gate circuit; and control voltage generation means for generating a control signal in response to a result of the comparison of said comparator means and applying the generated control signal to control said first power voltage control means, thereby constituting a phase locked-loop so as to stabilize the frequency of the output of the ring oscillator circuit; (b) a second CMOS gate circuit to which a signal to be pulse count detected is applied, the second CMOS gate circuit forming a delay circuit and comprising an even number of CMOS gates in series, wherein the second CMOS gate circuit includes second power voltage control means for controlling an operation power voltage applied to the second CMOS gate circuit thereby to control an amount of delay of the second CMOS gate circuit, and wherein said control signal generated by the phase locked-loop means is applied to the second voltage control means to set the delay of the second CMOS gate circuit; (c) an exclusive OR gate having one input receiving an output from said second CMOS gate circuit and a second input receiving the signal to be pulse count detected; and (d) a lowpass filter circuit for receiving the output of said exclusive OR gate and outputting a signal as the output of the pulse count detection circuit.
Claim 2
Dependent Claim
350 words
A pulse count detection circuit comprising: (a) phase locked-loop means for producing a control signal including: a ring oscillator circuit including a first CMOS gate circuit having an input terminal to which a binary input signal to be delayed is applied and an output terminal, a first power voltage control means for controlling an operation power voltage applied to the first CMOS gate circuit thereby to control an amount of delay of the first CMOS gate circuit and a feedback path for connecting said output of said first CMOS gate circuit back to said input of said first CMOS gate circuit; reference signal generation means for generating a reference signal of constant frequency; comparison means for comparing the phase of said reference signal to the phase of the output of said first CMOS gate circuit; and control voltage generation means for generating a control signal in response to a result of the comparison of said comparator means and applying the generated control signal to control said first power voltage control means, thereby constituting a phase locked-loop so as to stabilize the frequency of the output of the ring oscillator circuit; (b) a second CMOS gate circuit to which a signal to be pulse count detected is applied, the second CMOS gate circuit forming a delay circuit and comprising an even number of CMOS gates in series, wherein the second CMOS gate circuit includes second power voltage control means for controlling an operation power voltage applied to the second CMOS gate circuit thereby to control an amount of delay of the second CMOS gate circuit, and wherein said control signal generated by the phase locked-loop means is applied to the second voltage control means to set the delay of the second CMOS gate circuit; (c) an exclusive OR gate having one input receiving an output from said second CMOS gate circuit and a second input receiving the signal to be pulse count detected; and (d) a lowpass filter circuit for receiving the output of said exclusive OR gate and outputting a signal as the output of the pulse count detection circuit.
Claim 3
Dependent Claim
319 words
A frequency modulation circuit comprising: (a) phase locked-loop means for producing a control signal, including: a ring oscillator circuit including a first CMOS gate circuit having an input terminal to which a binary input signal to be delayed is applied and an output terminal, a first power voltage control means for controlling an operation power voltage applied to the first CMOS gate circuit thereby to control an amount of delay of the first CMOS gate circuit and a feedback path for connecting said output of said first CMOS gate circuit back to said input of said first CMOS gate circuit; reference signal generation means for generating a reference signal of constant frequency; comparison means for comparing the phase of said reference signal to the phase of the output of said first CMOS gate circuit; and control voltage generation means for generating a control signal in response to a result of the comparison of said comparator means and applying the generated control signal to control said first power voltage control means of said first CMOS gate circuit, thereby constituting a phase locked-loop so as to stabilize the frequency of the output of the ring oscillator circuit; (b) a second CMOS gate circuit comprising plural stages of CMOS gates in a loop, wherein the second CMOS gate circuit includes second power voltage control means for controlling an operation power voltage applied to the second CMOS gate circuit thereby to control an amount of delay of the second CMOS gate circuit, wherein said control signal generated by the phase locked-loop means is applied to the second voltage control means; and (c) means for receiving a modulation input signal and applying a signal corresponding to the modulation input signal to the second control voltage means to modulate the operation power voltage applied to the second CMOS gate circuit, wherein a frequency modulated output is derived from a predetermined output of the CMOS gates.
Claim 4
Dependent Claim
319 words
A frequency modulation circuit comprising: (a) phase locked-loop means for producing a control signal, including: a ring oscillator circuit including a first CMOS gate circuit having an input terminal to which a binary input signal to be delayed is applied and an output terminal, a first power voltage control means for controlling an operation power voltage applied to the first CMOS gate circuit thereby to control an amount of delay of the first CMOS gate circuit and a feedback path for connecting said output of said first CMOS gate circuit back to said input of said first CMOS gate circuit; reference signal generation means for generating a reference signal of constant frequency; comparison means for comparing the phase of said reference signal to the phase of the output of said first CMOS gate circuit; and control voltage generation means for generating a control signal in response to a result of the comparison of said comparator means and applying the generated control signal to control said first power voltage control means of said first CMOS gate circuit, thereby constituting a phase locked-loop so as to stabilize the frequency of the output of the ring oscillator circuit; (b) a second CMOS gate circuit comprising plural stages of CMOS gates in a loop, wherein the second CMOS gate circuit includes second power voltage control means for controlling an operation power voltage applied to the second CMOS gate circuit thereby to control an amount of delay of the second CMOS gate circuit, wherein said control signal generated by the phase locked-loop means is applied to the second voltage control means; and (c) means for receiving a modulation input signal and applying a signal corresponding to the modulation input signal to the second control voltage means to modulate the operation power voltage applied to the second CMOS gate circuit, wherein a frequency modulated output is derived from a predetermined output of the CMOS gates.
Claim 5
Dependent Claim
38 words
A circuit as defined in claim 1, wherein said first and second CMOS gate circuits comprise a series of CMOS gates each including a pair of complementary MOS transistors with interconnected gates which receive a common input signal.
Claim 6
Dependent Claim
38 words
A circuit as defined in claim 2, wherein said first and second CMOS gate circuits comprise a series of CMOS gates each including a pair of complementary MOS tranistors with interconnected gates which receive a common input signal.
Claim 7
Dependent Claim
29 words
A circuit as defined in claim 3 wherein said CMOS gates of said first and second CMOS gate circuits are formed on a same substrate under a same environment.
Claim 8
Dependent Claim
29 words
A circuit as defined in claim 4 wherein said CMOS gates of said first and second CMOS gate circuits are formed on a same substrate under a same environment.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-01-28 | 1994-07-30 | 1995-01-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-01-28 | 1998-07-30 | 1999-01-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-01-28 | 2002-07-30 | 2003-01-29 | $7700.00 | Window Closed / Lapsed |