US5022056A
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US
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Method and structure for digital phase synchronization
Assignee: National Semiconductor Corp
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Filing: 1989-10-23
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Granted: 1991-06-04
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Expires: 2009-10-23
Abstract
Abstract A novel method and structure is taught for synchronizing a received digital data stream to the receiver clock. A plurality of delay lines; are used to provide a plurality of delayed input signals, which are then compared with the receiver clock signal in order to determine which of the delayed input signals is closest in phase to the receiver clock signal. Once this determination is made, a multiplexer is used to select the appropriate one of the plurality of delayed input signals for use by the receiver. In an alternative embodiment, a plurality of delay lines are used to provide a plurality of delayed clock signals, which are then compared with the receiver input signal in order to determine which of the delayed clock signals is closest in phase to the receiver input signal. Once this determination is made, a multiplexer is used to select the appropriate one of the plurality of delayed clock signals for use by the receiver.
Inventors
- 👤 Richard D. Henderson
- 👤 Frederick K. Yin Leung
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 02:24
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H04L7/0337; H04L7/0338; H04L7/04; H04L7/041; H04L7/044
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
220 words
A phase synchronization circuit comprising: an input port for receiving an input signal; a clock input lead for receiving an input signal; a plurality of N delay means, each having an associated time delay unrelated to said clock signal, each said delay means not having absolute accuracy requirements with respect to each other or with respect to said clock signal, for providing a plurality of delayed input signals in response to said input signal; a plurality of N phase detector means, each having an input lead connected to receive an associated one of said delayed input signals, a clock input lead for receiving said clock signal, and an output signal for providing an indication of the phase relation between its associated one of said delayed input signals and said clock signal; decoder means for receiving said output signals from said phase detector means and in response thereto determining which one of said delayed input signals has a desired phase relationship with said clock signal, said decoder means comprising a plurality of exclusive OR gates, each of said exclusive OR gates having a first input lead connected to receive the output signals of two of said phase detector means; and selector means for selecting said one of said delayed input signals which has said desired phase relationship with said clock signal.
Claim 2
Dependent Claim
220 words
A phase synchronization circuit comprising: an input port for receiving an input signal; a clock input lead for receiving an input signal; a plurality of N delay means, each having an associated time delay unrelated to said clock signal, each said delay means not having absolute accuracy requirements with respect to each other or with respect to said clock signal, for providing a plurality of delayed input signals in response to said input signal; a plurality of N phase detector means, each having an input lead connected to receive an associated one of said delayed input signals, a clock input lead for receiving said clock signal, and an output signal for providing an indication of the phase relation between its associated one of said delayed input signals and said clock signal; decoder means for receiving said output signals from said phase detector means and in response thereto determining which one of said delayed input signals has a desired phase relationship with said clock signal, said decoder means comprising a plurality of exclusive OR gates, each of said exclusive OR gates having a first input lead connected to receive the output signals of two of said phase detector means; and selector means for selecting said one of said delayed input signals which has said desired phase relationship with said clock signal.
Claim 3
Dependent Claim
41 words
A method as in claim 1 wherein said one of said delayed input signals which has said desired phase relationship with said clock signal is the one of said delayed input signals which is closest in phase to said clock signal.
Claim 4
Dependent Claim
19 words
A phase synchronization circuit as in claim 1 wherein said phase detector means each comprise a D flip flop.
Claim 5
Dependent Claim
17 words
A phase synchronization circuit as in claim 1 which further comprises detection means comprising a storage element.
Claim 6
Dependent Claim
27 words
A phase synchronization circuit as in claim 1 wherein said selector means comprises a 1 of N selector, where N is the number of delayed input signals.
Claim 7
Dependent Claim
53 words
A phase synchronization circuit as in claim 1 wherein said delay means are connected in series such that the delayed input signal provided by a selected one of said delay means is delayed by an amount equal to the sum of said selected delay means plus the delays provided by preceding delay means.
Claim 8
Dependent Claim
20 words
A phase synchronization circuit as in claim 6 wherein said plurality of delay means each provide approximately the same delay.
Claim 9
Dependent Claim
22 words
A phase synchronization circuit as in claim 6 wherein said plurality of delay means do not each provide approximately the same delay.
Claim 10
Independent Claim
168 words
A method for phase synchronization comprising the steps of: receiving an input signal carrying data at a specified frequency; receiving a clock signal of said specified frequency; providing a plurality of delayed clock signals in response to said clock signal, each of said delayed clock signals being delayed from said clock signal by an associated period of time unrelated to said clock signal, said associated periods of time not having absolute accuracy requirements with respect to each other or with respect to said clock signal; selecting the one of said plurality of delayed clock signals that has a desired phase relationship with said input signal by using said selected delayed input signal to cause the approximate center of a data bit in said selected delayed input signal to correspond to a selected edge of said clock signal at which sampling of said data in said selected delayed input signal occurs; and using said selected one of said delayed clock signals to detect said data on said input signal.
Claim 11
Independent Claim
168 words
A method for phase synchronization comprising the steps of: receiving an input signal carrying data at a specified frequency; receiving a clock signal of said specified frequency; providing a plurality of delayed clock signals in response to said clock signal, each of said delayed clock signals being delayed from said clock signal by an associated period of time unrelated to said clock signal, said associated periods of time not having absolute accuracy requirements with respect to each other or with respect to said clock signal; selecting the one of said plurality of delayed clock signals that has a desired phase relationship with said input signal by using said selected delayed input signal to cause the approximate center of a data bit in said selected delayed input signal to correspond to a selected edge of said clock signal at which sampling of said data in said selected delayed input signal occurs; and using said selected one of said delayed clock signals to detect said data on said input signal.
Claim 12
Dependent Claim
41 words
A method as in claim 9 wherein said one of said delayed input signals which has said desired phase relationship with said clock signal is the one of said delayed input signals which is closest in phase to said clock signal.
Claim 13
Dependent Claim
217 words
A phase synchronization circuit comprising: an input port for receiving an input signal; a clock input lead for receiving a clock signal; a plurality of delay means, each having an associated time delay unrelated to said clock signal, each said delay means not having absolute accuracy requirements with respect to each other or with respect to said clock signal, for providing a plurality of delayed clock signals in response to said clock signal; a plurality of phase detector means, each having a clock input lead connected to receive an associated one of said delayed clock signals, an input lead for receiving said input signal, and an output signal for providing an indication of the phase relation between its associated one of said delayed clock signals and said input signal; decoder means for receiving said output signals from said phase detector means and in response thereto determining which one of said delayed clock signals has a desired phase relationship with said input signal, said decoder means comprising a plurality of exclusive OR gates, each of said exclusive OR gates having a first input lead connected to receive the output signals of two of said phase detector means; and selector means for selecting said one of said delayed clock signals as said desired phase relationship with said input signal.
Claim 14
Dependent Claim
217 words
A phase synchronization circuit comprising: an input port for receiving an input signal; a clock input lead for receiving a clock signal; a plurality of delay means, each having an associated time delay unrelated to said clock signal, each said delay means not having absolute accuracy requirements with respect to each other or with respect to said clock signal, for providing a plurality of delayed clock signals in response to said clock signal; a plurality of phase detector means, each having a clock input lead connected to receive an associated one of said delayed clock signals, an input lead for receiving said input signal, and an output signal for providing an indication of the phase relation between its associated one of said delayed clock signals and said input signal; decoder means for receiving said output signals from said phase detector means and in response thereto determining which one of said delayed clock signals has a desired phase relationship with said input signal, said decoder means comprising a plurality of exclusive OR gates, each of said exclusive OR gates having a first input lead connected to receive the output signals of two of said phase detector means; and selector means for selecting said one of said delayed clock signals as said desired phase relationship with said input signal.
Claim 15
Dependent Claim
19 words
A phase synchronization circuit as in claim 11 wherein said phase detector means each comprise a D flip flop.
Claim 16
Dependent Claim
27 words
A phase synchronization circuit as in claim 11 wherein said selector means comprises a 1 of N selector where N is the number of delayed clock signals.
Claim 17
Dependent Claim
53 words
A phase synchronization circuit as in claim 11 wherein said delay means are connected in series such that the delayed clock signal provided by a selected one of said delay means is delayed by an amount equal to the sum of said selected delay means plus the delays provided by preceding delay means.
Claim 18
Dependent Claim
20 words
A phase synchronization circuit as in claim 14 wherein said plurality of delay means each provide approximately the same delay.
Claim 19
Dependent Claim
22 words
A phase synchronization circuit as in claim 14 wherein said plurality of delay means do not each provide approximately the same delay.
Claim 20
Dependent Claim
17 words
A phase synchronization circuit as in claim 11 which further comprises detection means comprising a storage element.
Claim 21
Independent Claim
166 words
A method for phase synchronization comprising the steps of: receiving an input signal carrying data at a specified frequency; providing a plurality of delayed input signals in response to said input signal, each of said delayed input signals being delayed from said input signal by an associated period of time unrelated to said specified frequency, said associated periods of time not having absolute accuracy requirements with respect to each other or to said specified frequency; receiving a clock signal of said specified frequency; selecting the one of said plurality of delayed input signals that has a desired phase relationship with said clock signal by using said selected delayed input signal to cause the approximate center of a data bit in said selected delayed input signal to correspond to a selected edge of said clock signal at which sampling of said data in said selected delayed input signal occurs; and using said selected one of said delayed input signals to detect said data on said input signal.
Claim 22
Independent Claim
166 words
A method for phase synchronization comprising the steps of: receiving an input signal carrying data at a specified frequency; providing a plurality of delayed input signals in response to said input signal, each of said delayed input signals being delayed from said input signal by an associated period of time unrelated to said specified frequency, said associated periods of time not having absolute accuracy requirements with respect to each other or to said specified frequency; receiving a clock signal of said specified frequency; selecting the one of said plurality of delayed input signals that has a desired phase relationship with said clock signal by using said selected delayed input signal to cause the approximate center of a data bit in said selected delayed input signal to correspond to a selected edge of said clock signal at which sampling of said data in said selected delayed input signal occurs; and using said selected one of said delayed input signals to detect said data on said input signal.
Claim 23
Dependent Claim
41 words
A method as in claim 18 wherein said one of said delayed input signals which has said desired phase relationship with said clock signal is the one of said delayed input signals which is closest in phase to said clock signal.
References Cited (Backward Citations)
US3423534A
Cited
US3440547A
Cited
US3908084A
Cited
US4010323A
Cited
US4012598A
Cited
US4229824A
Cited
US4359770A
Cited
US4617679A
Cited
US4672639A
Cited
US4627080A
Cited
US4860323A
Cited
US4821296A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-06-03 | 1994-12-03 | 1995-06-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-06-03 | 1998-12-03 | 1999-06-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-06-03 | 2002-12-03 | 2003-06-04 | $7700.00 | Window Closed / Lapsed |