Adaptive timing circuit

Claim 2

An adaptive timing circuit comprising means for periodically sampling a received signal at sampling times so as to form a sample sequence, said sequence comprising a plurality of samples with each sample having an amplitude, means for selecting one threshold value from a plurality of threshold values, said selected threshold value being the threshold value closest to the amplitude of one sample in said sequence, means for comparing the amplitude of said one sample and said selected threshold value, and means responsive to said comparison and said sample sequence for driving future sampling times toward optimum sampling times only when said samples in said sequence have successively increasing amplitudes or when said samples in said sequence have successively decreasing amplitudes.

Claim 3

The circuit of claim 1 wherein said received signal forms a signal-eye pattern over time and said optimum sampling times coincide with said signal-eye pattern.

Claim 4

The circuit of claim 2 wherein said optimum sampling time coincides with the center of said signal-eye pattern.

Claim 5

The circuit of claim 1 wherein said sequence comprises three successive signal samples.

Claim 6

The circuit of claim 4 wherein said one sample is the middlemost sample in said sequence.

Claim 7

The circuit of claim 1 wherein said received signal is amplitude modulated and carries information on at least two discrete amplitude levels.

Claim 8

The circuit of claim 1 wherein said sampling times are controlled by clock signals and said driving means varies the timing of said clock signals.

Claim 9

The circuit of claim 7 wherein said clock signals are extracted from said received signal using an external clock recovery circuitry.

Claim 10

The circuit of claim 7 wherein said clock signals are generated by an oscillator.

Claim 11

The circuit of claim 8 wherein said driving means comprises a programmable phase shifter which shifts the phase of said clock signals relative to a reference clock.

Claim 12

The circuit of claim 10 wherein said programmable phase shifter maintains a predetermined phase shift between said clock signals and said reference clock in response to a control signal applied to said driving means.

Claim 13

An adaptive timing circuit comprising means for periodically sampling a received signal at sampling times so as to form a succession of samples with each sample having an amplitude represented by a multibit word, first memory means, addressed by each multibit word, for reading out one threshold value from a plurality of threshold values, each threshold value being a plurality of bits and said threshold value read out being the threshold value closest to the addressing multibit word, means for forming a difference between said plurality of bits of said read out threshold value and the associated first memory means multibit word address, and second memory means, addressed by said difference and predetermined bits of the associated first memory means multibit word address and predetermined bits of the first memory means multibit word addresses preceding and succeeding the associated multibit word address, for reading out an adjustment signal which varies future sampling times, said adjustment signal being read out only when said preceding associated and succeeding multibit word addresses respectively represent successively increasing or successively decreasing amplitudes.

Claim 14

An adaptive timing circuit comprising means for periodically sampling a received signal at sampling times so as to form a succession of samples with each sample having an amplitude represented by a multibit word, first memory means, addressed by each multibit word, for reading out one threshold value from a plurality of threshold values, each threshold value being a plurality of bits and said threshold value read out being the threshold value closest to the addressing multibit word, means for forming a difference between said plurality of bits of said read out threshold value and the associated first memory means multibit word address, and second memory means, addressed by said difference and predetermined bits of the associated first memory means multibit word address and predetermined bits of the first memory means multibit word addresses preceding and succeeding the associated multibit word address, for reading out an adjustment signal which varies future sampling times, said adjustment signal being read out only when said preceding associated and succeeding multibit word addresses respectively represent successively increasing or successively decreasing amplitudes.