Digital phase lock loop circuit

Claim 2

A circuit for producing a sampling clock signal for sampling an input data pulse signal, comprising: a reference clock pulse generator generating a reference clock pulse signal; first means responsive to a phase control signal for producing a phase-shifted reference clock signal from said reference clock pulse signal to obtain a sampling clock signal; second means responsive to an input data pulse signal for producing a first comparison signal only during a first interval within each one bit period of said input data pulse signal; third means responsive to said input data pulse signal for producing a second comparison signal only during a second interval within each one bit period of said input data pulse signal, said first and second intervals being shorter than said one bit period of said input data pulse signal and separated from each other to leave a third interval therebetween; a phase comparator for comparing said sampling clock signal with said first and second comparison signals and producing a first error signal when said sampling clock signal occurs during said first interval and a second error signal when said sampling clock signal occurs during said second interval, said phase comparator producing no error signal when said sampling clock occurs during said third interval; and fourth means responsive to said first and second error signals for producing said phase control signal, whereby a predetermined phase relationship is maintained between said sampling clock signal and said input data pulse signal.

Claim 3

The circuit as claimed in claim 1, wherein said first means includes phase shift means responsive to said reference clock signal for producing a plurality of phase shifted clock signals and selection means responsive to said phase control signal for selecting one of said phase shifted clock signals, the selected phase shifted clock signal being employed as said sampling clock signal.

Claim 4

The circuit as claimed in claim 1, wherein said phase comparator includes a first flip-flop circuit having a clock terminal supplied with said sampling clock signal and a data terminal supplied with said first comparison signal and producing said first error signal, and a second flip-flop circuit having a clock terminal supplied with said sampling clock signal and a data terminal supplied with said second comparison signal and producing said second error signal.

Claim 5

The circuit as claimed in claim 3, wherein said fourth means includes a counter counting in a first direction in response to said first error signal and in a second direction in response to said second error signal.

Claim 6

A circuit as claimed in claim 1, wherein said second and third means together comprise means for generating a waveform shaped data pulse from said received data, means for generating a plurality of delayed versions of said waveform-shaped data pulse, means for combining said waveform-shaped data pulse with a selected one of said delayed versions of said waveform-shaped data pulse to generate said first comparison signal, and means for combining said waveform-shaped data pulse with a different one of said delayed versions of said waveform-shaped data pulse to generate said second comparison signal.

Claim 7

A circuit for maintaining a predetermined phase relationship between an input data pulse signal and a sampling clock signal, comprising: a reference clock generator for generating a reference clock signal; phase shift means responsive to said reference clock signal for producing a plurality of phase shifted clock signals; first means responsive to said input data pulse signal for producing a first pulse signal from said input data pulse signal, the leading and trailing edges within one cycle period of said first pulse signal defining a first interval within each one bit period of said input data pulse signal; second means responsive to said input data pulse signal for producing a second pulse signal from said input data pulse signal, the leading and trailing edges within one cycle period of said second pulse signal defining a second interval within each one bit period of said input data pulse signal, said first and second intervals being shorter than said one bit period of said input data pulse signal and separated from each other to leave a third interval therebetween; third means responsive to a selection signal for selecting one of said phase shifted clock signals as said sampling clock signal; first phase comparing means responsive to said sampling clock signal and said first pulse signal for producing a first error signal when one of the leading and trailing edges of said sampling clock signal appears during said first interval; second phase comparing means responsive to said sampling clock signal and said second pulse signal for producing a second error signal when said one of the leading and trailing edges of said sampling clock signal appears during said second interval; and fourth means responsive to said first or second error signals for changing said selection signal, said third means selecting another phase shifted clock signal in response to the changed selection signal.

Claim 8

A circuit for maintaining a predetermined phase relationship between an input data pulse signal and a sampling clock signal, comprising: a reference clock generator for generating a reference clock signal; phase shift means responsive to said reference clock signal for producing a plurality of phase shifted clock signals; first means responsive to said input data pulse signal for producing a first pulse signal from said input data pulse signal, the leading and trailing edges within one cycle period of said first pulse signal defining a first interval within each one bit period of said input data pulse signal; second means responsive to said input data pulse signal for producing a second pulse signal from said input data pulse signal, the leading and trailing edges within one cycle period of said second pulse signal defining a second interval within each one bit period of said input data pulse signal, said first and second intervals being shorter than said one bit period of said input data pulse signal and separated from each other to leave a third interval therebetween; third means responsive to a selection signal for selecting one of said phase shifted clock signals as said sampling clock signal; first phase comparing means responsive to said sampling clock signal and said first pulse signal for producing a first error signal when one of the leading and trailing edges of said sampling clock signal appears during said first interval; second phase comparing means responsive to said sampling clock signal and said second pulse signal for producing a second error signal when said one of the leading and trailing edges of said sampling clock signal appears during said second interval; and fourth means responsive to said first or second error signals for changing said selection signal, said third means selecting another phase shifted clock signal in response to the changed selection signal.

Claim 9

The circuit as claimed in claim 6, wherein said fourth means includes an up/down counter having an up terminal supplied with said first error signal and a down terminal supplied with said second error signal, the count value of said up/down counter being utilized as said selection signal.

Claim 10

A circuit for producing a sampling clock signal for sampling an input data pulse signal, comprising: phase shift means responsive to said input data pulse signal for producing a plurality of phase shifted data pulse signals, logic gate means responsive to a selected one or ones of said phase shifted data pulse signals for producing first and second non-overlapping pulses during respective non-overlapping first and second intervals in each one bit cycle period of said input data pulse signal; first phase comparing means responsive to said sampling clock signal and said first pulse for producing a first error signal when one of the leading and trailing edges of said sampling clock signal appears during said first interval; a second phase comparing means responsive to said sampling clock signal and said second pulse for producing a second error signal when said one of the leading and trailing edges of said sampling clock signal appears during said second interval; a reference clock generator generating a reference clock signal; means responsive to said reference clock signal for producing said sampling clock signal, and means responsive to said first error signal for advancing the phase of said sampling clock signal and responsive to said second error signal for delaying the phase of said sampling clock signal, whereby said sampling clock signal and said input data signal maintain a predetermined phase relationship therebetween.

Claim 11

A circuit for producing a sampling clock signal for sampling an input data pulse signal, comprising: phase shift means responsive to said input data pulse signal for producing a plurality of phase shifted data pulse signals, logic gate means responsive to a selected one or ones of said phase shifted data pulse signals for producing first and second non-overlapping pulses during respective non-overlapping first and second intervals in each one bit cycle period of said input data pulse signal; first phase comparing means responsive to said sampling clock signal and said first pulse for producing a first error signal when one of the leading and trailing edges of said sampling clock signal appears during said first interval; a second phase comparing means responsive to said sampling clock signal and said second pulse for producing a second error signal when said one of the leading and trailing edges of said sampling clock signal appears during said second interval; a reference clock generator generating a reference clock signal; means responsive to said reference clock signal for producing said sampling clock signal, and means responsive to said first error signal for advancing the phase of said sampling clock signal and responsive to said second error signal for delaying the phase of said sampling clock signal, whereby said sampling clock signal and said input data signal maintain a predetermined phase relationship therebetween.

Claim 12

A digital phase lock loop circuit comprising: a clock generator for generating a reference clock signal; first phase shifting means responsive to said reference clock signal for producing a plurality of phase shifted clock signals; selecting means responsive to a selection signal for selecting one of said phase shifted clock signals as a sampling clock signal; second phase shifting means responsive to an input data pulse signal for producing a plurality of phase shifted data pulse signals, first logic gate means responsive to a first selected one or ones of said phase shifted data pulse signals for producing a first pulse signal, a first logic level period within one cycle period of said first pulse signal defining a first interval within each one bit period of said input data pulse signal; second logic gate means responsive to a second selected one or ones of said phase shifted data pulse signals for producing a second pulse signal, the first logic level period within one cycle period of said second pulse signal defining a second interval within each one bit period of said input data pulse signal, the first logic level period of said first pulse signal being separated from the first logic level period of said second pulse signal to form a third interval within each one bit period of said input data pulse signal between said first and second intervals; phase comparing means responsive to said sampling clock signal and said first and second pulse signals for producing a first error signal when one of the leading and trailing edges of said sampling clock signal appears during the first interval and a second error signal when said one of said leading and trailing edges of said sampling clock signal appears during the second interval, and means responsive to any one of said first and second error signals for changing said selection signal, whereby said selecting means selects another one of said phase shifted clock signals as said sampling signal to maintain a predetermined phase relationship between said sampling clock signal and said input data pulse signal.

Claim 13

A digital phase lock loop circuit comprising: a clock generator for generating a reference clock signal; first phase shifting means responsive to said reference clock signal for producing a plurality of phase shifted clock signals; selecting means responsive to a selection signal for selecting one of said phase shifted clock signals as a sampling clock signal; second phase shifting means responsive to an input data pulse signal for producing a plurality of phase shifted data pulse signals, first logic gate means responsive to a first selected one or ones of said phase shifted data pulse signals for producing a first pulse signal, a first logic level period within one cycle period of said first pulse signal defining a first interval within each one bit period of said input data pulse signal; second logic gate means responsive to a second selected one or ones of said phase shifted data pulse signals for producing a second pulse signal, the first logic level period within one cycle period of said second pulse signal defining a second interval within each one bit period of said input data pulse signal, the first logic level period of said first pulse signal being separated from the first logic level period of said second pulse signal to form a third interval within each one bit period of said input data pulse signal between said first and second intervals; phase comparing means responsive to said sampling clock signal and said first and second pulse signals for producing a first error signal when one of the leading and trailing edges of said sampling clock signal appears during the first interval and a second error signal when said one of said leading and trailing edges of said sampling clock signal appears during the second interval, and means responsive to any one of said first and second error signals for changing said selection signal, whereby said selecting means selects another one of said phase shifted clock signals as said sampling signal to maintain a predetermined phase relationship between said sampling clock signal and said input data pulse signal.

Claim 14

The digital phase lock loop circuit as claimed in claim 9, wherein each of said first and second phase shifting means includes a phase delay line circuit having a plurality of taps each producing its respective phase shifted signal.

Claim 15

A circuit for producing a sampling clock signal for sampling an input data pulse signal, comprising: a reference clock pulse generator for generating a reference clock pulse signal; first means responsive to a phase control signal for producing a phase-shifted reference clock signal from said reference clock pulse signal to obtain a sampling clock signal; second means responsive to a received data signal for generating normalized data signal pulses of uniform pulse width; third means for producing a first comparison signal only during a first interval within each one bit period of said normalized data signal pulses; fourth means for producing a second comparison signal only during a second interval within each one bit period of said input data pulse signal, said first and second intervals being shorter than said one bit period of said normalized data signal pulse and separated from each other to have a third interval therebetween; a phase comparator for comparing said sampling clock signal with said first and second comparison signals and producing a first error signal when said sampling clock signal occurs during said first interval and a second error signal when said sampling clock signal occurs during said second interval, said phase comparator producing no error signal when said sampling clock occurs during said third interval; and fifth means responsive to said first and second error signals for producing said phase control signal, whereby a predetermined phase relationship is maintained between said sampling clock signal and said input data pulse signal.

Claim 16

A circuit for producing a sampling clock signal for sampling an input data pulse signal, comprising: a reference clock pulse generator for generating a reference clock pulse signal; first means responsive to a phase control signal for producing a phase-shifted reference clock signal from said reference clock pulse signal to obtain a sampling clock signal; second means responsive to a received data signal for generating normalized data signal pulses of uniform pulse width; third means for producing a first comparison signal only during a first interval within each one bit period of said normalized data signal pulses; fourth means for producing a second comparison signal only during a second interval within each one bit period of said input data pulse signal, said first and second intervals being shorter than said one bit period of said normalized data signal pulse and separated from each other to have a third interval therebetween; a phase comparator for comparing said sampling clock signal with said first and second comparison signals and producing a first error signal when said sampling clock signal occurs during said first interval and a second error signal when said sampling clock signal occurs during said second interval, said phase comparator producing no error signal when said sampling clock occurs during said third interval; and fifth means responsive to said first and second error signals for producing said phase control signal, whereby a predetermined phase relationship is maintained between said sampling clock signal and said input data pulse signal.