US5345449A — Clock generation

Claim 1

Independent Claim 203 words

An integrated circuit comprising: a terminal connected to receive a first clock signal at a first rate, said first clock signal comprising a plurality of clock edges; a multiplexor connected to receive a plurality of incoming data streams in parallel at said first rate under the control of said first clock signal, the multiplexor being controllable by a high rate clock signal to output that data serially at a second, higher rate; a processing device coupled to receive data output from the multiplexor at the higher rate and controllable by said high rate clock signal to process that data; and clock generation circuitry connected to receive said first clock signal at said first rate and operable to produce therefrom said high rate clock signal to be supplied to the processing device and to the multiplexor, wherein said clock generation circuitry is operable to produce, on receipt of each clock edge of the first clock signal, a predetermined number of clock edges to constitute said high rate clock signal whereby said high rate clock signal is synchronized with said first clock signal, said predetermined number being controllable to control a multiplication factor by which the high rate clock signal exceeds the first clock signal.

Claim 2

Dependent Claim 203 words

An integrated circuit comprising: a terminal connected to receive a first clock signal at a first rate, said first clock signal comprising a plurality of clock edges; a multiplexor connected to receive a plurality of incoming data streams in parallel at said first rate under the control of said first clock signal, the multiplexor being controllable by a high rate clock signal to output that data serially at a second, higher rate; a processing device coupled to receive data output from the multiplexor at the higher rate and controllable by said high rate clock signal to process that data; and clock generation circuitry connected to receive said first clock signal at said first rate and operable to produce therefrom said high rate clock signal to be supplied to the processing device and to the multiplexor, wherein said clock generation circuitry is operable to produce, on receipt of each clock edge of the first clock signal, a predetermined number of clock edges to constitute said high rate clock signal whereby said high rate clock signal is synchronized with said first clock signal, said predetermined number being controllable to control a multiplication factor by which the high rate clock signal exceeds the first clock signal.

Claim 3

Dependent Claim 102 words

An integrated circuit as claimed in claim 1 wherein the clock generation circuitry comprises: a plurality of sequentially connected delay devices, a first one of which is coupled to receive the first clock signal, each delay device being operable to produce a trigger signal and an output signal at a predetermined time after receiving a trigger signal from the previously connected delay device; control circuitry operable to provide a common control signal to said delay devices for controlling said predetermined time interval; and output circuitry coupled to receive the output signals of the delay devices to produce therefrom said second clock signal.

Claim 4

Dependent Claim 47 words

An integrated circuit as claimed in claim 2 in which the control circuitry is connected in a feedback loop so as to be responsive to an error signal resulting from comparison of the first clock signal with the trigger signal output by the last connected delay device.

Claim 5

Dependent Claim 53 words

An integrated circuit as claimed in claim 2 in which the output circuitry has a plurality of inputs for receiving respective ones of the output signals of the delay devices and is operable to change the state of its own output signal on receipt of each said output signal of the delay device.

Claim 6

Dependent Claim 37 words

An integrated circuit as claimed in claim 2 in which each delay device comprises analogue timing circuitry and digital control circuitry thereby to achieve a substantially linear response of the predetermined time interval to the control circuitry.

Claim 7

Dependent Claim 128 words

An integrated circuit as claimed in claim 5 in which the analogue timing circuitry comprises a controllable switch element responsive to a reset signal to change from a first state to a second state, a capacitive device connected to be charged up when said controllable switch element is in said first state, and a comparator connected to receive as a first input signal the voltage across the capacitive device, and as a second input signal said control voltage from said control circuitry, and producing as an output a timing signal in dependence on said first and second input signals and the digital control circuitry being connected to receive said timing signal and to provide in response thereto the trigger signal of the delay device and said reset signal.

Claim 8

Dependent Claim 33 words

An integrated circuit as claimed in claim 2 with p delay devices and circuitry for selecting n of the p delay devices (where n≦p) for use in generation of the second clock signal.

Claim 9

Dependent Claim 186 words

An integrated circuit as claimed in claim 2 wherein the output circuitry for producing the second clock signal comprises a plurality of generation units connected respectively to receive the output signals of the delay devices, the generation units being individually connectable to a common output line and each generation unit having three states: a neutral state in which the output line is examined; a negative drive state in which a negative going pulse is driven onto the output line; and a positive drive state in which a positive going pulse is driven onto the output line, the second clock signal thereby being generated on the output line as follows: prior to receipt of a trigger signal by its associated delay device a generation unit is in its neutral state and when a delay device receives a trigger signal, the generation unit associated with that delay device responds to the output signal of that delay device to adopt one of its positive and negative drive states in dependence on the state of the second clock signal just prior to the change of state of that generation unit.

Claim 10

Dependent Claim 52 words

An integrated circuit as claimed in claim 3 wherein said output circuitry has a plurality of inputs for receiving respective ones of said output signals of said delay devices and is operable to change the state of its own output signal on receipt of each said output signal of the delay device.

Claim 11

Dependent Claim 36 words

An integrated circuit as claimed in claim 3 wherein each delay device comprises analog timing circuitry and digital control circuitry thereby to achieve a substantially linear response of the predetermined time interval to the control circuitry.

Claim 12

Dependent Claim 36 words

An integrated circuit as claimed in claim 1, in which the clock generation circuitry comprises circuitry for setting the ratio of the frequency of the high rate signal to the frequency of the first clock signal.

Claim 13

Dependent Claim 50 words

An integrated circuit as claimed in claim 11, in which the clock generation circuitry comprises a plurality of delay devices and wherein the circuitry for setting the ratio of the frequencies comprises circuitry for selecting from said plurality of delay devices of predetermined set thereof thereby to control said ratio.

Claim 14

Independent Claim 91 words

A method of synchronizing a multiplexor and a processing device on an integrated circuit, the method comprising the steps of: controlling a stream of data supplied to the multiplexor with a first clock signal at a first rate; supplying the first clock signal to clock generation circuitry on the integrated circuit, said clock generation circuitry being operable to produce from said first clock signal a high rate clock signal which is an integral multiple of said first rate and synchronized thereto; and controlling the multiplexor using the high rate clock signal.

Claim 15

Independent Claim 91 words

A method of synchronizing a multiplexor and a processing device on an integrated circuit, the method comprising the steps of: controlling a stream of data supplied to the multiplexor with a first clock signal at a first rate; supplying the first clock signal to clock generation circuitry on the integrated circuit, said clock generation circuitry being operable to produce from said first clock signal a high rate clock signal which is an integral multiple of said first rate and synchronized thereto; and controlling the multiplexor using the high rate clock signal.

Claim 16

Dependent Claim 36 words

A method of synchronizing a multiplexor as claimed in claim 13 further comprising the step of programming the ratio of the frequency of the high rate clock signal to the frequency of the first clock signal.

Claim 17

Dependent Claim 149 words

An integrated circuit comprising: a terminal connected to receive a first clock signal at a first rate; clock generation circuitry connected to receive said first clock signal at said first rate and operable to produce therefrom a high rate clock signal which is an integral multiple of said first rate and synchronized with said first rate; a multiplexor having a plurality of inputs connected to receive respective incoming data streams in parallel under the control of said first clock signal at said first rate, the multiplexor being connected to receive said high rate clock signal and to output said data serially at the rate of said high rate clock signal; and a processing device coupled to receive said data output from the multiplexor at the rate of said high rate clock signal and having a terminal for receiving said high rate clock signal to control processing of that data.

Claim 18

Dependent Claim 149 words

An integrated circuit comprising: a terminal connected to receive a first clock signal at a first rate; clock generation circuitry connected to receive said first clock signal at said first rate and operable to produce therefrom a high rate clock signal which is an integral multiple of said first rate and synchronized with said first rate; a multiplexor having a plurality of inputs connected to receive respective incoming data streams in parallel under the control of said first clock signal at said first rate, the multiplexor being connected to receive said high rate clock signal and to output said data serially at the rate of said high rate clock signal; and a processing device coupled to receive said data output from the multiplexor at the rate of said high rate clock signal and having a terminal for receiving said high rate clock signal to control processing of that data.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1997-09-05	1998-03-07	1998-09-06	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2001-09-05	2002-03-07	2002-09-06	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2005-09-05	2006-03-07	2006-09-06	$7700.00	Window Closed / Lapsed

Clock generation

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