US3631464A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital parallel to serial converter
Assignee: Link Flight Simulation Corp
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Filing: 1969-03-21
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Granted: 1971-12-28
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Expires: 1989-03-21
Abstract
Abstract The disclosed embodiment of the present invention is a digital parallel to serial converter for a television raster display which employs a phase-locked loop for controlling the conversion rate. The disclosed converter is formed of a register which receives data in parallel form, a plurality of transfer gates for transferring data out of the register, and a frequency controlled gating circuit for enabling the transfer gates. The frequency controlled gating circuit is formed of a voltage controlled oscillator having an output connected to a counter, which is, in turn, connected to a decoder from which the gating pulses are derived for enabling the transfer gates. A flip-flop is connected to the counter and to a clock, such that the DC average value of an output thereof forms a feedback control for the oscillator.
Inventors
- 👤 Roger C Dahlberg
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 07:44
CPC Classifications
H; H03; H03M; H03M9/00
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
163 words
A parallel to serial converter disposed for receiving information in parallel format which is made available at a first rate susceptible of variation, comprising a. a register disposed for receiving the information in parallel format therein, b. a plurality of transfer gates each having an input connected to a respective output of said register, c. means for generating gating pulses at a predetermined rate and supplying said pulses to said transfer gates to transfer the information from parallel form in said register into serial form, d. means for developing an error signal in accordance with the difference between said first rate and said predetermined rate, said generating means being responsive to said error signal for altering the predetermined rate, and e. said generating means including an oscillator, said information including timing pulses having a rate equal to said first rate, said developing means being responsive to an output of said oscillator and to said timing pulses for controlling the frequency of said oscillator.
Claim 2
Dependent Claim
163 words
A parallel to serial converter disposed for receiving information in parallel format which is made available at a first rate susceptible of variation, comprising a. a register disposed for receiving the information in parallel format therein, b. a plurality of transfer gates each having an input connected to a respective output of said register, c. means for generating gating pulses at a predetermined rate and supplying said pulses to said transfer gates to transfer the information from parallel form in said register into serial form, d. means for developing an error signal in accordance with the difference between said first rate and said predetermined rate, said generating means being responsive to said error signal for altering the predetermined rate, and e. said generating means including an oscillator, said information including timing pulses having a rate equal to said first rate, said developing means being responsive to an output of said oscillator and to said timing pulses for controlling the frequency of said oscillator.
Claim 3
Dependent Claim
37 words
A parallel to serial converter as defined in claim 1, wherein said developing means generates a signal which is proportional to the phase disparity between an output pulse of said oscillator and one of said timing pulses.
Claim 4
Dependent Claim
59 words
A parallel to serial converter as defined in claim 2, wherein said developing means includes a bistable device having one input coupled to an output of said oscillator and another input connected to receive said timing pulses, and means for generating a DC voltage proportional in amplitude to the average voltage of an output signal of said bistable device.
Claim 5
Dependent Claim
204 words
A parallel to serial converter disposed for receiving information in parallel format which is made available at a first rate susceptible of variation, comprising a. a register disposed for receiving the information in parallel format therein, b. a plurality of transfer gates each having an input connected to a respective output of said register, c. means for generating gating pulses at a predetermined rate and supplying said pulses to said transfer gates to transfer the information from parallel form in said register into serial form, d. means for developing an error signal in accordance with the difference between said first rate and said predetermined rate, said generating means being responsive to said error signal for altering the predetermined rate, and e. said generating means including an oscillator, means for frequency dividing an output of said oscillator for generating said gating signals, said developing means including a bistable device having one input connected to an output of said dividing means, said information including timing pulses having a rate equal to said first rate and being connected to another input of said bistable device, and means for generating a DC voltage proportional in amplitude to the average voltage of an output signal of said bistable device.
Claim 6
Dependent Claim
204 words
A parallel to serial converter disposed for receiving information in parallel format which is made available at a first rate susceptible of variation, comprising a. a register disposed for receiving the information in parallel format therein, b. a plurality of transfer gates each having an input connected to a respective output of said register, c. means for generating gating pulses at a predetermined rate and supplying said pulses to said transfer gates to transfer the information from parallel form in said register into serial form, d. means for developing an error signal in accordance with the difference between said first rate and said predetermined rate, said generating means being responsive to said error signal for altering the predetermined rate, and e. said generating means including an oscillator, means for frequency dividing an output of said oscillator for generating said gating signals, said developing means including a bistable device having one input connected to an output of said dividing means, said information including timing pulses having a rate equal to said first rate and being connected to another input of said bistable device, and means for generating a DC voltage proportional in amplitude to the average voltage of an output signal of said bistable device.
Claim 7
Dependent Claim
65 words
A parallel to serial converter as defined in claim 4, wherein said oscillator includes a flip-flop and an output connected to one input of said flip-flop, and a second gate having one input connected to another output of said flip-flop and an output connected to another input of said flip-flop, the other input of each of said gates being connected to a source of voltage.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-12-27 | 1975-06-28 | 1975-12-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-12-27 | 1979-06-28 | 1979-12-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-12-27 | 1983-06-28 | 1983-12-28 | $7700.00 | Window Closed / Lapsed |