EP0219604A2
Expired / Lapsed
EP
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Apparatus and method for producing signals related in phase to a clock signal
Assignee: HP Inc
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Filing: 1986-06-06
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Granted: —
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Expires: 2006-06-06
Abstract
Abstract An apparatus and method are described for generating a plurality of clock edges from a reference clock signal. The clock edges which are generated are locked in phase with the reference clock signal. The edges may be at any integral or non-integral multiple of the reference clock frequency.
Inventors
- 👤 John R. Spencer
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-25 21:33
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/15; H03K5/15013; H03K5/15026; H03K5/1504
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
219 words
An apparatus for generating a clock edge referenced to a clock signal, characterized by first variable delay means (421) for delaying an input signal (410) to generate an output signal (411), the output signal (411) being the input signal delayed by a first delay interval and the first generated clock edge, the input signal connected to the clock signal, the first delay interval responsive to a control signal (420); second variable delay means (422) for delaying an input signal (411) to generate an output signal (412), the output signal (412) being the input signal delayed by a second delay interval, the input signal connected to the output signal of the first variable delay means (421), the second delay interval responsive to the control signal (420); comparator means (405) for comparing a first signal (409) to a second signal (412) and generating a control signal (420), the first signal connected to the clock signal, the second signal (412) connected to the output of the second variable delay means (422), the control signal (420) connected to first and second variable delay means (421,422) for increasing the first and second delay intervals if the second signal (412) occurs before the first signal (409) or decreasing the first and second delay intervals if the first signal (409) occurs before the second signal (412).
Claim 2
Independent Claim
219 words
An apparatus for generating a clock edge referenced to a clock signal, characterized by first variable delay means (421) for delaying an input signal (410) to generate an output signal (411), the output signal (411) being the input signal delayed by a first delay interval and the first generated clock edge, the input signal connected to the clock signal, the first delay interval responsive to a control signal (420); second variable delay means (422) for delaying an input signal (411) to generate an output signal (412), the output signal (412) being the input signal delayed by a second delay interval, the input signal connected to the output signal of the first variable delay means (421), the second delay interval responsive to the control signal (420); comparator means (405) for comparing a first signal (409) to a second signal (412) and generating a control signal (420), the first signal connected to the clock signal, the second signal (412) connected to the output of the second variable delay means (422), the control signal (420) connected to first and second variable delay means (421,422) for increasing the first and second delay intervals if the second signal (412) occurs before the first signal (409) or decreasing the first and second delay intervals if the first signal (409) occurs before the second signal (412).
Claim 3
Dependent Claim
83 words
An apparatus as in claim 1 for generating a second clock edge characterized by third variable delay means (423) for delaying an input signal (412) to generate an output signal (413), the output signal being the input signal delayed by a third delay interval and the second generated clock edge, the input signal connected to the clock signal, the third delay interval responsive to the control signal (420), the output signal connected to the input (410) of the first variable delay means (421).
Claim 4
Independent Claim
82 words
A method for generating a clock edge referenced to a clock signal, characterized by delaying the clock signal in proportion to a control signal to generate a first signal; delaying the first signal in proportion to a control signal to generate a second signal; comparing the second signal to the clock signal; and adjusting the control signal to increase the delay if the second signal leads the clock signal or the decrease the delay if the second signal lags the clock signal.
Claim 5
Independent Claim
82 words
A method for generating a clock edge referenced to a clock signal, characterized by delaying the clock signal in proportion to a control signal to generate a first signal; delaying the first signal in proportion to a control signal to generate a second signal; comparing the second signal to the clock signal; and adjusting the control signal to increase the delay if the second signal leads the clock signal or the decrease the delay if the second signal lags the clock signal.
Claim 6
Dependent Claim
48 words
A method as in claim 3 for generating additional clock edges, characterized by delaying the second signal in proportion to a control signal to generate a third signal and supplying the third signal in place of the second signal to the step of comparing and step of adjusting.
Claim 7
Independent Claim
219 words
An apparatus for generating a clock edge referenced to a clock signal and alternate clock signal, characterized by first variable delay means (421) for delaying an input signal (410) to generate an output signal (411) and the first clock edge, the output signal being the input signal delayed by a first delay interval, the input signal connected to the clock signal, the first delay interval responsive to a control signal (420); second variable delay means (422) for delaying an input signal (411) to generate an output signal (412), the output signal being the input signal delayed by a second delay interval, the input signal connected to the output signal of the first variable delay means (421), the second delay interval responsive to the control signal (420); comparator means (405) for comparing a first signal to a second signal and generating a control signal (420), the first signal connected to the alternate clock signal (409), the second signal connected to the output of the second variable delay means (422), the control signal (420) connected to first and second variable delay means (421,422) for increasing the first and second delay interval if the second signal (412) occurs before the first signal (409) or decreasing the first and second delay interval if the first signal (412) occurs before the second signal (409).
Claim 8
Independent Claim
219 words
An apparatus for generating a clock edge referenced to a clock signal and alternate clock signal, characterized by first variable delay means (421) for delaying an input signal (410) to generate an output signal (411) and the first clock edge, the output signal being the input signal delayed by a first delay interval, the input signal connected to the clock signal, the first delay interval responsive to a control signal (420); second variable delay means (422) for delaying an input signal (411) to generate an output signal (412), the output signal being the input signal delayed by a second delay interval, the input signal connected to the output signal of the first variable delay means (421), the second delay interval responsive to the control signal (420); comparator means (405) for comparing a first signal to a second signal and generating a control signal (420), the first signal connected to the alternate clock signal (409), the second signal connected to the output of the second variable delay means (422), the control signal (420) connected to first and second variable delay means (421,422) for increasing the first and second delay interval if the second signal (412) occurs before the first signal (409) or decreasing the first and second delay interval if the first signal (412) occurs before the second signal (409).
Claim 9
Dependent Claim
100 words
An apparatus as in claim 5, wherein the comparator means further comprises: a comparison generating means (901) for comparing a first signal to a second signal and generate a first flag if the rising edge of the first signal leads the rising edge of the second signal, a second flag if the rising edge of the first signal lags the rising edge of the second signal, and a third flag if the rising edge occurs at the same time asthe rising edge of the second signal; and a filter means (902) for filter the flags generated by the comparison means.
Claim 10
Dependent Claim
22 words
An apparatus as in claim 1 or 5, characterized in that the first delay interval is equal to the second delay interval.
Claim 11
Dependent Claim
74 words
An apparatus as in claim 1 or 5 for generating high current clock edges characterized by third variable delay means (423) for delaying an input signal (412) to generate an output signal (413), the output signal being the input signal delayed by the first delay interval, the input, signal connected to the clock signal (409), the first delay interval responsive to the control signal (420), the output signal being the high current clock edge.
Claim 12
Independent Claim
92 words
A method for generating a clock edge referenced to a reference clock signal and an alternate clock signal, characterized by delaying the reference clock signal in proportion to a control signal to generate a first signal; delaying the first signal in proportion to a control signal to generate a second signal; comparing the second signal to the alternate clock signal; and adjusting the control signal to increase the delay if the second signal leads the alternate clock signal or the decrease the delay if the second signal lags the alternate clock signal.
Claim 13
Independent Claim
92 words
A method for generating a clock edge referenced to a reference clock signal and an alternate clock signal, characterized by delaying the reference clock signal in proportion to a control signal to generate a first signal; delaying the first signal in proportion to a control signal to generate a second signal; comparing the second signal to the alternate clock signal; and adjusting the control signal to increase the delay if the second signal leads the alternate clock signal or the decrease the delay if the second signal lags the alternate clock signal.
References Cited (Backward Citations)
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