Three-dimensional non-volatile memory

Claim 2

A memory structure comprising: a semiconductor material having an upper surface, said upper surface comprising a first substantially lateral and planar surface, a sidewall surface, and a second substantially lateral and planar surface, said first surface being laterally and vertically displaced with respect to said second surface, the semiconductor material at said sidewall surface being substantially free of ion impact damage; a source region extending into said semiconductor material from said first surface; a drain region extending into said semiconductor material from said second surface; a first layer of insulator material disposed on said sidewall surface; a floating gate disposed on said first layer of insulator material; a second layer of insulator material disposed on said floating gate; and a conductive layer disposed on said second layer of insulator material, said second layer of insulator material separating said floating gate and said conductive layer.

Claim 3

The memory structure of claim 1, wherein said conductive layer is a word line extending along said sidewall surface in a first dimension, said memory structure further comprising: a bit line extending in a second dimension substantially perpendicular to said first dimension, said bit line being coupled to said drain region.

Claim 4

The memory structure of claim 2, wherein said floating gate is a layer of polysilicon.

Claim 5

The memory structure of claim 3, wherein said word line comprises polysilicon.

Claim 6

The memory structure of claim 3, wherein said second layer of insulator material comprises a first layer of oxide, a layer of nitride, and a second layer of oxide.

Claim 7

A memory structure comprising: a semiconductor material of a first conductivity type having an upper surface, said upper surface having first and second elongated depressions which extend in a first dimension, each of said elongated depressions having opposing steep sidewalls and a bottom surface, the semiconductor material at said steep sidewalls being substantially free of ion impact damage; a first insulator layer disposed on said sidewalls of said first and second depressions; a first plurality of strips of a conductive layer, a respective one each of said first plurality of strips extending in said first dimension over a respective one of said sidewalls and being insulated from said sidewalls; a second plurality of strips of a conductive layer, each of said second plurality of strips extending substantially parallel to the others of said second plurality of strips and extending in a second dimension substantially perpendicular to said first dimension, each of said second plurality of strips crossing over said first plurality of strips and crossing over said first and second depressions; a plurality of floating gates, a respective one of said floating gates being disposed near each respective location where one of said second plurality of strips crosses one of said first plurality of strips, each floating gate being disposed between one of said first plurality of strips and the sidewall over which said strip is disposed; a second insulator layer, each floating gate being insulated from the one of said second plurality of strips which crosses over said each floating gate; first and second elongated conductive regions of a second conductivity type opposite said first conductivity type, said first elongated conductive region extending into said bottom surface of said first depression, said second conductive region extending into said bottom surface of said second depression; and a plurality of third conductive regions of said second conductivity type extending into said semiconductor material between said first and second depressions, a respective one of said third conductive regions being disposed underneath and being coupled to a respective one of said second plurality of strips.

Claim 8

A memory structure comprising: a semiconductor material of a first conductivity type having an upper surface, said upper surface having first and second elongated depressions which extend in a first dimension, each of said elongated depressions having opposing steep sidewalls and a bottom surface, the semiconductor material at said steep sidewalls being substantially free of ion impact damage; a first insulator layer disposed on said sidewalls of said first and second depressions; a first plurality of strips of a conductive layer, a respective one each of said first plurality of strips extending in said first dimension over a respective one of said sidewalls and being insulated from said sidewalls; a second plurality of strips of a conductive layer, each of said second plurality of strips extending substantially parallel to the others of said second plurality of strips and extending in a second dimension substantially perpendicular to said first dimension, each of said second plurality of strips crossing over said first plurality of strips and crossing over said first and second depressions; a plurality of floating gates, a respective one of said floating gates being disposed near each respective location where one of said second plurality of strips crosses one of said first plurality of strips, each floating gate being disposed between one of said first plurality of strips and the sidewall over which said strip is disposed; a second insulator layer, each floating gate being insulated from the one of said second plurality of strips which crosses over said each floating gate; first and second elongated conductive regions of a second conductivity type opposite said first conductivity type, said first elongated conductive region extending into said bottom surface of said first depression, said second conductive region extending into said bottom surface of said second depression; and a plurality of third conductive regions of said second conductivity type extending into said semiconductor material between said first and second depressions, a respective one of said third conductive regions being disposed underneath and being coupled to a respective one of said second plurality of strips.

Claim 9

The memory structure of claim 6, wherein said plurality of floating gates are polysilicon gates, said first plurality of strips comprises polysilicon, said second plurality of strips are metal strips.

Claim 10

The memory structure of claim 7, wherein said first plurality of strips are word lines and wherein said second plurality of strips are bit lines.

Claim 11

The memory structure of claim 6, wherein said elongated depressions have opposing gradually sloping sidewalls in addition to said steep sidewalls.

Claim 12

The memory structure of claim 6, further comprising: a plurality of oxide spacers, part of said oxide spacers being disposed on side-edges of said floating gates and on side-edges of said first plurality of strips.

Claim 13

The memory structure of claim 6, wherein each of said first and second elongated conductive regions comprises: a first relatively shallow region disposed under one of said first plurality of strips disposed over a sidewall of a depression; a second relatively shallow region disposed under another of said first plurality of strips disposed over the opposing sidewall of said depression; and a relatively deep region disposed between said first and second relatively shallow regions and contacting said first and second relatively shallow regions.