Circuitry and method for selecting a drain programming voltage for a nonvolatile memory

Claim 2

A nonvolatile memory residing on a single substrate, comprising: (A) a memory array having at least a memory cell, wherein the memory cell includes a drain region, a source region, a control gate, and a floating gate; (B) a drain programming voltage generation circuit coupled to a programming voltage source and the drain region of the memory cell for providing a drain programming voltage to the drain region of the memory cell during programming of the memory cell; (C) a control circuit coupled to the drain programming voltage generation circuit for controlling the drain programming voltage generation circuit to cause the drain programming voltage to vary with respect to a programming ability of the memory cell such that the memory cell is programmed to be within a predetermined range of a predetermined threshold voltage with a predetermined gate programming voltage for a predetermined programming time, wherein the control circuit stores a control value that determines the voltage level of the drain programming voltage, wherein the voltage level of the drain programming voltage is changed by changing the control value in the control circuit, wherein the control value can be changed after the control value is set in the control circuit.

Claim 3

The nonvolatile memory of claim 1, wherein the drain programming voltage generation circuit further comprises a voltage setting circuit for setting the voltage level of the drain programming voltage in accordance with the control value, wherein voltage setting circuit is coupled to receive the control value from the control circuit.

Claim 4

The nonvolatile memory of claim 2, wherein the voltage setting circuit of the drain programming voltage generation circuit further comprises a plurality of transistors connected in parallel, wherein each of the plurality of transistors has a gate coupled to the control circuit, wherein the control circuit selectively turns on a particular combination of the plurality of transistors in accordance with the control value from the control circuit.

Claim 5

The nonvolatile memory of claim 3, further comprising (i) current mirror circuit coupled to the programming voltage source for providing a substantially constant first current; (ii) a source follower circuit coupled to (1) the programming voltage source, (2) the current mirror circuit, (3) the voltage setting circuit, and (4) an output of the drain programming voltage generation circuit for providing the first-current to the voltage setting circuit and for charging and settling the output node of the drain programming voltage generation circuit to the drain programming voltage, wherein the source follower circuit acts as a positive feedback loop to help the output node to be quickly charged to the drain programming voltage.

Claim 6

The nonvolatile memory of claim 1, wherein the memory cell is an electrically erasable and electrically programmable read only memory cell.

Claim 7

The nonvolatile memory of claim 1, wherein the memory cell can store a plurality of data bits at one time.

Claim 8

The nonvolatile memory of claim 1, wherein the predetermined range is approximately 1 volt.

Claim 11

The method of claim 8, further comprising the step of selectively turning on a particular combination of the plurality of transistors of a voltage setting circuit of the drain programming voltage generation circuit in accordance with the first value such that the drain programming voltage generation circuit generates the drain programming voltage in accordance with the first value.

Claim 12

The method of claim 8 wherein the nonvolatile memory is an electrically erasable and electrically programmable read only memory.

Claim 13

The method of claim 8, wherein the predetermined range is approximately 1 volt.

Claim 14

A nonvolatile memory residing on a single substrate, comprising: (A) a memory array having at least a first memory transistor coupled to a bit line, wherein the first memory transistor includes a drain region coupled to the bit line, a source region, a control gate, and a floating gate, wherein the first memory transistor further includes an effective channel length: (B) a drain programming voltage generation circuit coupled to a programming voltage source and the bit line for providing a drain programming voltage to the drain region of the first memory transistor via the bit line during programming of the first memory transistor, wherein the drain programming voltage generation circuit further comprises (i) a voltage setting circuit for setting the voltage level of the drain programming voltage, wherein the voltage setting circuit further comprises a second memory, transistor that has an effective channel length substantially equal to that of the first memory, transistor of the memory, array such that the drain programming voltage generation circuit generates the drain programming voltage that also varies with respect to the effective channel length of the first memory transistor; (ii) a current mirror circuit coupled to the programming voltage source for providing a substantially constant first current; (iii) a source follower circuit coupled to (1) the programming voltage source, (2) the current mirror circuit, (3) the voltage setting circuit, and (4) an output of the drain programming voltage generation circuit for providing the first current to the voltage setting circuit and for charging and settling the output node of the drain programming voltage generation circuit to the drain programming voltage, wherein the source follower circuit acts as a positive feedback loop to help the output node to be quickly charged to the drain programming voltage.

Claim 15

A nonvolatile memory residing on a single substrate, comprising: (A) a memory array having at least a first memory transistor coupled to a bit line, wherein the first memory transistor includes a drain region coupled to the bit line, a source region, a control gate, and a floating gate, wherein the first memory transistor further includes an effective channel length: (B) a drain programming voltage generation circuit coupled to a programming voltage source and the bit line for providing a drain programming voltage to the drain region of the first memory transistor via the bit line during programming of the first memory transistor, wherein the drain programming voltage generation circuit further comprises (i) a voltage setting circuit for setting the voltage level of the drain programming voltage, wherein the voltage setting circuit further comprises a second memory, transistor that has an effective channel length substantially equal to that of the first memory, transistor of the memory, array such that the drain programming voltage generation circuit generates the drain programming voltage that also varies with respect to the effective channel length of the first memory transistor; (ii) a current mirror circuit coupled to the programming voltage source for providing a substantially constant first current; (iii) a source follower circuit coupled to (1) the programming voltage source, (2) the current mirror circuit, (3) the voltage setting circuit, and (4) an output of the drain programming voltage generation circuit for providing the first current to the voltage setting circuit and for charging and settling the output node of the drain programming voltage generation circuit to the drain programming voltage, wherein the source follower circuit acts as a positive feedback loop to help the output node to be quickly charged to the drain programming voltage.

Claim 16

The nonvolatile memory of claim 12, wherein the current mirror circuit further comprises a third memory transistor that has an effective channel length substantially equal to that of the first memory transistor of the memory array and that of the second memory transistor of the voltage setting circuit.

Claim 17

A nonvolatile memory, comprising: (A) a memory array having at least a first memory transistor coupled to a bit line, wherein the first memory transistor includes a drain region coupled to the bit line, a source region, a control gate, and a floating gate, wherein the first memory transistor further includes an effective channel length; (B) a drain programming voltage generation circuit coupled to a programming voltage source and the bit line for providing a drain programming voltage to the drain region of the first memory transistor via the bit line during programming of the first memory transistor, wherein the drain programming voltage generation circuit has a controllable resistance that varies in accordance with the effective channel length of the first memory transistor such that the drain programming voltage generation circuit generates the drain programming voltage that also varies with respect to the effective channel length of the first memory transistor, wherein the drain programming voltage generation circuit further comprises (i) a plurality of transistors connected in parallel for providing the controllable resistance, wherein the controllable resistance is selected by selectively turning on a particular combination of the plurality of transistors.

Claim 18

A nonvolatile memory, comprising: (A) a memory array having at least a first memory transistor coupled to a bit line, wherein the first memory transistor includes a drain region coupled to the bit line, a source region, a control gate, and a floating gate, wherein the first memory transistor further includes an effective channel length; (B) a drain programming voltage generation circuit coupled to a programming voltage source and the bit line for providing a drain programming voltage to the drain region of the first memory transistor via the bit line during programming of the first memory transistor, wherein the drain programming voltage generation circuit has a controllable resistance that varies in accordance with the effective channel length of the first memory transistor such that the drain programming voltage generation circuit generates the drain programming voltage that also varies with respect to the effective channel length of the first memory transistor, wherein the drain programming voltage generation circuit further comprises (i) a plurality of transistors connected in parallel for providing the controllable resistance, wherein the controllable resistance is selected by selectively turning on a particular combination of the plurality of transistors.

Claim 19

The nonvolatile memory of claim 14, further comprising a control circuit coupled to the drain programming voltage generation circuit, wherein each of the plurality of transistors has a gate coupled to the control circuit, wherein the control circuit selectively turns on a particular combination of the plurality of transistors in accordance with a control value stored in the control circuit.

Claim 20

The nonvolatile memory of claim 20, wherein the drain programming voltage generation circuit further comprises (ii) a current mirror circuit coupled to the programming voltage source for providing a substantially constant first current; (iii) a source follower circuit coupled to (1) the programming voltage source, (2) the current mirror circuit, (3) the plurality of transistors, and (4) an output of the drain programming voltage generation circuit for providing the first current to the plurality of transistors and for charging and settling the output node of the drain programming voltage generation circuit to the drain programming voltage, wherein the source follower circuit acts as a positive feedback loop to help the output node to be quickly charged to the drain programming voltage.