US5928343A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory module having memory devices containing internal device ID registers and method of initializing same
Assignee: Rambus Inc
•
Filing: 1998-06-16
•
Granted: 1999-07-27
•
Expires: 2018-06-16
Abstract
Abstract A method and apparatus for assigning identification values to memories. A master resets identifiers of a first memory and a second memory by sending a reset signal on a line that is coupled in a daisy-chained manner to the first and second memories and also coupled to the master. The master places a first identification value on a data bus coupled to the master and to the first and second memories. The first memory stores the first identification value on the data bus as an identifier for the first memory when the master sends a first storage signal to the first memory via the daisy-chained line. The master places a second identification value on the data bus. The second memory stores the second identification value on the data bus as an identifier for the second memory when the master sends a second storage signal to the second memory via the daisy-chained line.
Inventors
- 👤 Michael Farmwald
- 👤 Mark Horowitz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 11:23
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1051; G11C7/1066; G06; G06F; G06F11/00; G06F11/006; G06F12/00; G06F12/02; G06F12/0215; G06F12/06; G06F12/0646; G06F12/0653; G06F12/0661; G06F12/0684; G06F13/00; G06F13/14; G06F13/16; G06F13/1605; G06F13/161; G06F13/1668; G06F13/1678; G06F13/1689; G06F13/1694; G06F13/36; G06F13/368; G06F13/376; G06F13/38; G06F13/42; G06F13/4204; G06F13/4234; G06F13/4239; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4076; G11C11/409; G11C11/4096; G11C29/00; G11C29/70; G11C29/88; G11C5/00; G11C5/02; G11C5/04; G11C5/06; G11C5/063; G11C5/066; G11C7/1006; G11C7/1012; G11C7/1015; G11C7/1045; G11C7/1057; G11C7/1069; G11C7/1072; G11C7/1078; G11C7/1084; G11C7/22; G11C7/222; G11C7/225; G11C8/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1048; G11C2207/00; G11C2207/10; G11C2207/105; G11C2207/108; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 34
Claim 1
Independent Claim
125 words
A method for assigning identification values to memories, comprising the steps of: (1) having a master reset identifiers of a first memory and a second memory by sending a reset signal on a line that is coupled in a daisy-chained manner to the first and second memories and also coupled to the master; (2) having a master send first and second identification values on the daisy-chained line to the first and second memories; (3) having the first memory store at a first predetermined time the first identification value on the daisy-chained line as an identifier for the first memory; (4) having the second memory store at a second predetermined time the second identification value on the daisy-chained line as an identifier for the second memory.
Claim 2
Independent Claim
125 words
A method for assigning identification values to memories, comprising the steps of: (1) having a master reset identifiers of a first memory and a second memory by sending a reset signal on a line that is coupled in a daisy-chained manner to the first and second memories and also coupled to the master; (2) having a master send first and second identification values on the daisy-chained line to the first and second memories; (3) having the first memory store at a first predetermined time the first identification value on the daisy-chained line as an identifier for the first memory; (4) having the second memory store at a second predetermined time the second identification value on the daisy-chained line as an identifier for the second memory.
Claim 3
Independent Claim
160 words
An apparatus for assigning identification values to memories, the apparatus comprising: (1) a daisy-chained line coupled to a master, a first memory and a second memory; (2) a data bus coupled to the master, the first memory, and the second memory; (3) reset circuitry for sending a reset signal from the master to the first and second memories via the daisy-chained line and for resetting identifiers of the first and second memories in response to the reset signal; (4) circuitry within the master for generating first and second identification values and sending them to the first and second memories via the daisy-chained line; (5) circuitry within the first memory for storing at a first predetermined time the first identification value on the daisy-chained line as an identifier for the first memory; and (6) circuitry within the second memory for storing at a second predetermined time the second identification value on the daisy-chained line as an identifier for the second memory.
Claim 4
Independent Claim
160 words
An apparatus for assigning identification values to memories, the apparatus comprising: (1) a daisy-chained line coupled to a master, a first memory and a second memory; (2) a data bus coupled to the master, the first memory, and the second memory; (3) reset circuitry for sending a reset signal from the master to the first and second memories via the daisy-chained line and for resetting identifiers of the first and second memories in response to the reset signal; (4) circuitry within the master for generating first and second identification values and sending them to the first and second memories via the daisy-chained line; (5) circuitry within the first memory for storing at a first predetermined time the first identification value on the daisy-chained line as an identifier for the first memory; and (6) circuitry within the second memory for storing at a second predetermined time the second identification value on the daisy-chained line as an identifier for the second memory.
Claim 5
Dependent Claim
207 words
A memory module having a plurality of memory devices, the memory module comprises: a bus having a plurality of signal lines including a reset signal line which is electrically connected to the plurality of memory devices; a first memory device including: at least one memory section having a plurality of memory cells which are accessed using address signals; an internal register to store an identification value to identify the first memory device on the bus; and interface circuitry, coupled to the bus, to receive a reset request via the reset signal line wherein, in response to a received reset request, the internal register in the first memory device stores the identification value which identifies the first memory device on the bus; and a second memory device including: at least one memory section having a plurality of memory cells which are accessed using address signals; an internal register to store an identification value to identify the second memory device on the bus; and interface circuitry, coupled to the bus, to receive a reset request via the reset signal line wherein, in response to a received reset request, the internal register in the second memory device stores the identification value which identifies the second memory device on the bus.
Claim 6
Dependent Claim
207 words
A memory module having a plurality of memory devices, the memory module comprises: a bus having a plurality of signal lines including a reset signal line which is electrically connected to the plurality of memory devices; a first memory device including: at least one memory section having a plurality of memory cells which are accessed using address signals; an internal register to store an identification value to identify the first memory device on the bus; and interface circuitry, coupled to the bus, to receive a reset request via the reset signal line wherein, in response to a received reset request, the internal register in the first memory device stores the identification value which identifies the first memory device on the bus; and a second memory device including: at least one memory section having a plurality of memory cells which are accessed using address signals; an internal register to store an identification value to identify the second memory device on the bus; and interface circuitry, coupled to the bus, to receive a reset request via the reset signal line wherein, in response to a received reset request, the internal register in the second memory device stores the identification value which identifies the second memory device on the bus.
Claim 7
Dependent Claim
74 words
The memory module of claim 3 wherein: the internal register of the first memory device stores a unique identification value to identify the first memory device from thy plurality of memory devices, including the second memory device, on the bus; and the internal register of the second memory device stores a unique identification value to identify the second memory device from the plurality of memory devices, including the first memory device, on the bus.
Claim 8
Dependent Claim
39 words
The memory module of claim 3 wherein the internal register of the first memory device stores an identification value to identify the first memory device and a plurality of memory devices, including the second memory device, on the bus.
Claim 9
Dependent Claim
28 words
The memory module of claim 3 wherein the bus includes a clock signal line for receiving an external clock signal and data lines for receiving the identification values.
Claim 10
Dependent Claim
26 words
The memory module of claim 6 wherein the first memory device includes a reset register coupled to the reset signal line to receive the reset signal.
Claim 11
Dependent Claim
36 words
The memory module of claim 7 wherein the reset register of the first memory device is clocked synchronously with respect to the external clock signal such that the reset signal is clocked through the reset register.
Claim 12
Dependent Claim
33 words
The memory module of claim 8 wherein the identification register of the first memory device stores the identification value while the reset signal is in the reset register of the first memory device.
Claim 13
Dependent Claim
52 words
The memory module of claim 9 wherein the internal register of the first memory device stores the identification value of the first memory device register after a predetermined number of clock cycles of the external clock signal and while the reset signal is in the reset register of the first memory device.
Claim 14
Dependent Claim
22 words
The memory module of claim 3 wherein the first and second memory devices receive the identification values on the reset signal line.
Claim 15
Dependent Claim
60 words
The memory module of claim 11 wherein the internal register of the first memory device stores the identification value which identifies the first memory device on the bus at a first predetermined time and the internal register of the second memory device stores the identification value which identifies the second memory device on the bus at a second predetermined time.
Claim 16
Dependent Claim
17 words
The memory module of claim 12 wherein the first and the second predetermined times are the same.
Claim 17
Dependent Claim
25 words
The memory module of claim 12 wherein the identification values are clocked along the reset signal line synchronously with respect to an external clock signal.
Claim 18
Dependent Claim
33 words
The memory module of claim 12 wherein the internal registers of the first and second memory device store the identification values after a predetermined number of clock cycles of an external clock signal.
Claim 19
Dependent Claim
31 words
The memory module of claim 12 wherein the first memory device includes a reset register coupled to the reset signal line to receive the identification value of the first memory device.
Claim 20
Dependent Claim
20 words
The memory module of claim 16 wherein the reset register is clocked synchronously with respect to an external clock signal.
Claim 21
Dependent Claim
33 words
The memory module of claim 16 wherein the identification register is coupled to the reset register to receive and store the identification value received by the reset register at the first predetermined time.
Claim 22
Dependent Claim
38 words
The memory module of claim 16 wherein the identification register is coupled to the reset register to receive and store the data in the reset register after a predetermined number of clock cycles of the external clock signal.
Claim 23
Dependent Claim
33 words
The memory module of claim 12 wherein the second memory device includes a reset register coupled to the reset signal line at an output of the reset register of the first memory device.
Claim 24
Dependent Claim
25 words
The memory module of claim 20 wherein the reset register of the second memory device is clocked synchronously with respect to the external clock signal.
Claim 25
Dependent Claim
31 words
The memory module of claim 21 wherein the identification register is coupled to the reset register to receive and store the data in the reset register at the second predetermined time.
Claim 26
Dependent Claim
19 words
The memory module of claim 22 wherein the first predetermined time and the second predetermined time are the same.
Claim 27
Independent Claim
226 words
A method of assigning identification values to a plurality of memory devices disposed on a memory module, the plurality of memory devices include a first memory device having a programmable register for storing an identification value and second memory device having a programmable register for storing an identification value, wherein the memory module includes a bus to electrically connect the first and the second memory devices, wherein the bus includes a plurality of signal lines including a reset signal line which electrically connects the first and the second memory devices, a clock signal line for receiving an external clock signal, and data lines for receiving first and second identification values, the method comprising: applying the first identification value on the data lines for a predetermined number of clock cycles of the external clock signal; applying a reset signal to the first memory device wherein, in response to the reset signal received by the first memory device, the programmable register in the first memory device stores the first identification value; applying the second information value on the data lines for the predetermined number of clock cycles of the external clock signal; and applying a reset signal to the second memory device wherein, in response to the reset signal received by the second memory device, the programmable register in the second memory device stores the second identification value.
Claim 28
Independent Claim
226 words
A method of assigning identification values to a plurality of memory devices disposed on a memory module, the plurality of memory devices include a first memory device having a programmable register for storing an identification value and second memory device having a programmable register for storing an identification value, wherein the memory module includes a bus to electrically connect the first and the second memory devices, wherein the bus includes a plurality of signal lines including a reset signal line which electrically connects the first and the second memory devices, a clock signal line for receiving an external clock signal, and data lines for receiving first and second identification values, the method comprising: applying the first identification value on the data lines for a predetermined number of clock cycles of the external clock signal; applying a reset signal to the first memory device wherein, in response to the reset signal received by the first memory device, the programmable register in the first memory device stores the first identification value; applying the second information value on the data lines for the predetermined number of clock cycles of the external clock signal; and applying a reset signal to the second memory device wherein, in response to the reset signal received by the second memory device, the programmable register in the second memory device stores the second identification value.
Claim 29
Dependent Claim
65 words
The method of claim 24 wherein: the first identification value is a unique identification value which identifies the first memory device from the plurality of memory devices, including the second memory device, on the bus; and the second identification value is a unique identification value which identifies the second memory device from the plurality of memory devices, including the first memory device, on the bus.
Claim 30
Dependent Claim
35 words
The method of claim 24 wherein the first identification value is a special identification value which identifies the first memory device and a plurality of memory devices, including the second memory device, on the bus.
Claim 31
Independent Claim
111 words
A method of assigning identification values to first and second memory devices disposed on a memory module having a bus which electrically connects the first and the second memory devices, wherein the bus includes a plurality of signal lines including a daisy-chained signal line which electrically connects the first and the second memory devices in a daisy-chained manner, the method comprising: applying first and second identification values on the daisy-chained signal line; storing the first identification value in a programmable register in the first memory device at a first predetermined time; and storing the second identification value in a programmable register in the second memory device at a second predetermined time.
Claim 32
Independent Claim
111 words
A method of assigning identification values to first and second memory devices disposed on a memory module having a bus which electrically connects the first and the second memory devices, wherein the bus includes a plurality of signal lines including a daisy-chained signal line which electrically connects the first and the second memory devices in a daisy-chained manner, the method comprising: applying first and second identification values on the daisy-chained signal line; storing the first identification value in a programmable register in the first memory device at a first predetermined time; and storing the second identification value in a programmable register in the second memory device at a second predetermined time.
Claim 33
Dependent Claim
55 words
The method of claim 27 wherein: the first identification value is a unique identification value which identifies the first memory device from the plurality of memory devices on the bus; and the second identification value is a unique identification value which identifies the second memory device from the plurality of memory devices on the bus.
Claim 34
Dependent Claim
30 words
The method of claim 27 wherein the first identification value is a special identification value which identifies the first memory device and a plurality of memory devices on the bus.
References Cited (Backward Citations)
US3633166A
Cited
US3691534A
Cited
US3740723A
Cited
US3771145A
Cited
US3771145B1
Cited
US3924241A
Cited
US3758761A
Cited
US3821715A
Cited
US3983537A
Cited
US3972028A
Cited
US3975714A
Cited
US3882470A
Cited
US4038648A
Cited
US3969706A
Cited
US4263650B1
Cited
US4263650A
Cited
US4007452A
Cited
US4099231A
Cited
US4494186A
Cited
US4191996A
Cited
US4333142A
Cited
US4375665A
Cited
US4247817A
Cited
US4205373A
Cited
US4234934A
Cited
US4315308A
Cited
US4249247A
Cited
US4354258A
Cited
US4286321A
Cited
US4306298A
Cited
US4443864A
Cited
US4385350A
Cited
US4468738A
Cited
US4373183A
Cited
US4355376A
Cited
US4945471A
Cited
US4493021A
Cited
US4630193A
Cited
US4481647A
Cited
US4458357A
Cited
US4513374A
Cited
US4500905A
Cited
US4811202A
Cited
US4595923A
Cited
US4481625A
Cited
US4480307A
Cited
US4488218A
Cited
US4470114A
Cited
US4449207A
Cited
US4761799A
Cited
US4519034A
Cited
US4513370A
Cited
US4608700A
Cited
US4571672A
Cited
US4770640A
Cited
US4649511A
Cited
US4656605A
Cited
US4646270A
Cited
US4570220A
Cited
US4882669A
Cited
US4635192A
Cited
US4660141A
Cited
US4745548A
Cited
US4654655A
Cited
US4766536A
Cited
US4775931A
Cited
US4566098A
Cited
US4649516A
Cited
US4675813A
Cited
US4860198A
Cited
US4933835A
Cited
US4862158A
Cited
US4757473A
Cited
US4779089A
Cited
US4858112A
Cited
US4965792A
Cited
US4785396A
Cited
US4719627A
Cited
US4706166A
Cited
US4803621A
Cited
US4785394A
Cited
US5117494A
Cited
US5021772A
Cited
US4818985A
Cited
US4764846A
Cited
US5056060A
Cited
US5038320A
Cited
US4837682A
Cited
US4937733A
Cited
US4831338A
Cited
US5051889A
Cited
US4964038A
Cited
US4947484A
Cited
US4920486A
Cited
US5093807A
Cited
US4954992A
Cited
US5083260A
Cited
US4975763A
Cited
US5193199A
Cited
US5220673A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-07-26 | 2003-01-25 | 2003-07-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-07-26 | 2007-01-25 | 2007-07-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-07-26 | 2011-01-25 | 2011-07-27 | $7700.00 | Window Closed / Lapsed |