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US5927992A
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Method of forming a dielectric in an integrated circuit
Assignee: STMicroelectronics lnc USA
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Filing: 1994-05-31
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Granted: 1999-07-27
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Expires: 2014-05-31
Abstract
Abstract A method is provided for forming an improved device dielectric of a semiconductor integrated circuit, and an integrated circuit formed according to the same. For scaling geometries for use in the submicron regime, a composite dielectric layer used as a device dielectric is formed over a plurality of active areas adjacent to a field oxide region. The composite dielectric layer is formed before the field oxide region is formed and comprises a non-porous silicon nitride layer. The non-porous silicon nitride layer preferably comprises a thin deposited silicon nitride layer overlying a thin nitridized region of the substrate. The silicon nitride layer is partially oxidized during the subsequent formation of a field oxide region between the plurality of active areas. An oxide layer may be formed over the silicon nitride layer before the formation of the field oxide region which will then be densified during the field oxide formation. The composite dielectric layer is then patterned and etched to form the dielectric portion of various integrated circuit devices.
Inventors
- 👤 Robert L. Hodges
- 👤 Frank R. Bryant
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:48
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/69; H10P14/694; H10P14/6943; H10P14/69433; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/01338; H10D64/0134; H10D64/01344; H10D64/60; H10D64/66; H10D64/68; H10D64/681; H10D64/685; H10D64/693; H10P14/61; H10P14/63; H10P14/6326; H10P14/6328; H10P14/6334; H10P14/65; H10P14/6502; H10P14/6512; H10P14/6516; H10P14/6518; H10P14/6519; H10P14/6522; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/0125; H10W10/0126; H10W10/10; H10W10/13; H10P14/692; H10P14/6921; H10P14/69215; Y; Y10; Y10S; Y10S438/00; Y10S438/954
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
100 words
A method of forming a portion of a semiconductor integrated circuit, comprising: forming a composite layer over a plurality of active regions on a surface of a substrate, wherein the composite layer comprises a silicon nitride layer having a thickness of between approximately 10-120 angstroms; forming a field oxide region between certain active regions, wherein during the formation of the field oxide, the upper surface of the silicon nitride layer is oxidized; forming an oxide layer over the silicon nitride layer before the field oxide region is formed; and patterning and etching the composite layer to form a device dielectric.
Claim 2
Independent Claim
100 words
A method of forming a portion of a semiconductor integrated circuit, comprising: forming a composite layer over a plurality of active regions on a surface of a substrate, wherein the composite layer comprises a silicon nitride layer having a thickness of between approximately 10-120 angstroms; forming a field oxide region between certain active regions, wherein during the formation of the field oxide, the upper surface of the silicon nitride layer is oxidized; forming an oxide layer over the silicon nitride layer before the field oxide region is formed; and patterning and etching the composite layer to form a device dielectric.
Claim 3
Dependent Claim
40 words
The method of claim 1, wherein the forming the silicon nitride layer step comprises the steps of: annealing an upper surface of the substrate in an ambient comprising nitrogen; and depositing a layer of silicon nitride over the annealed substrate.
Claim 4
Dependent Claim
13 words
The method of claim 2, wherein the annealing step comprises a furnace anneal.
Claim 5
Dependent Claim
14 words
The method of claim 2, wherein the annealing step comprises a rapid thermal anneal.
Claim 6
Dependent Claim
20 words
The method of claim 2, wherein the annealing step forms a nitridized layer of about 5 to about 70 angstroms.
Claim 7
Dependent Claim
14 words
The method of claim 2, wherein the silicon nitride layer is formed by LPCVD.
Claim 8
Dependent Claim
22 words
The method of claim 2, wherein the silicon nitride layer is formed to a depth of about 5 to about 50 angstroms.
Claim 9
Dependent Claim
13 words
The method of claim 1, wherein the oxide layer is formed by LPCVD.
Claim 10
Dependent Claim
21 words
The method of claim 1, wherein the oxide layer is formed at a temperature of between approximately 800 to 1000° C.
Claim 11
Dependent Claim
21 words
The method of claim 1, wherein the oxide layer is formed to a depth of about 5 to about 50 angstroms.
Claim 12
Dependent Claim
24 words
The method of claim 1, further comprising: forming a polysilicon layer over the oxide layer; and forming a nitride layer over the polysilicon layer.
Claim 13
Dependent Claim
34 words
The method of claim 11, wherein the polysilicon layer is formed to a depth wherein the upper surface of the polysilicon layer is substantially planar with the upper surface of the field oxide region.
Claim 14
Independent Claim
181 words
A method of forming a portion of a semiconductor integrated circuit, comprising: annealing a region of an upper surface of a substrate in an ambient comprising nitrogen forming a nitridized layer; forming a layer of silicon nitride over the annealed region, wherein the nitride layer and the nitridized layer form a composite dielectric having a thickness of between approximately 10-120 angstroms; patterning and etching an opening in the composite dielectric to expose a portion of the substrate, wherein the composite dielectric can act as a mask barrier overlying the substrate during subsequent processing steps; forming a field oxide region in the opening, wherein the formation of the field oxide region oxidizes an upper surface of the composite dielectric; patterning and etching the composite dielectric to form a portion of an integrated circuit device; and forming an oxide layer over the silicon nitride layer before the field oxide region is formed, wherein the oxide and nitride layers and the nitridized layer form the composite dielectric, and wherein the oxide layer is formed by LPCVD at temperatures between approximately 500 to 1000° C.
Claim 15
Independent Claim
181 words
A method of forming a portion of a semiconductor integrated circuit, comprising: annealing a region of an upper surface of a substrate in an ambient comprising nitrogen forming a nitridized layer; forming a layer of silicon nitride over the annealed region, wherein the nitride layer and the nitridized layer form a composite dielectric having a thickness of between approximately 10-120 angstroms; patterning and etching an opening in the composite dielectric to expose a portion of the substrate, wherein the composite dielectric can act as a mask barrier overlying the substrate during subsequent processing steps; forming a field oxide region in the opening, wherein the formation of the field oxide region oxidizes an upper surface of the composite dielectric; patterning and etching the composite dielectric to form a portion of an integrated circuit device; and forming an oxide layer over the silicon nitride layer before the field oxide region is formed, wherein the oxide and nitride layers and the nitridized layer form the composite dielectric, and wherein the oxide layer is formed by LPCVD at temperatures between approximately 500 to 1000° C.
Claim 16
Dependent Claim
36 words
The method of claim 13, further comprising the steps of: forming a polysilicon layer over the composite dielectric before the composite dielectric is patterned and etched; and etching the polysilicon layer along with the composite dielectric.
Claim 17
Dependent Claim
37 words
The method of claim 14, wherein the polysilicon layer and composite dielectric are formed to a depth wherein the upper surface of the polysilicon layer is substantially planar with the upper surface of the field oxide region.
Claim 18
Independent Claim
139 words
A method of forming a portion of a semiconductor integrated circuit; comprising the steps of: annealing a region of an upper surface of a substrate in an ambient comprising nitrogen forming a nitridized layer; forming a layer of silicon nitride over the annealed region; forming an oxide over the silicon nitride layer, wherein the oxide and nitride layers and the nitridized layer form a composite dielectric; patterning and etching an opening in the composite dielectric to expose a portion of the substrate, wherein the composite dielectric can act as a mask barrier overlying the substrate during subsequent processing steps; forming a field oxide region in the opening, wherein the formation of the field oxide region densifies the oxide layer of the composite dielectric; patterning and etching the resulting composite dielectric to form a portion of an integrated circuit device.
Claim 19
Independent Claim
139 words
A method of forming a portion of a semiconductor integrated circuit; comprising the steps of: annealing a region of an upper surface of a substrate in an ambient comprising nitrogen forming a nitridized layer; forming a layer of silicon nitride over the annealed region; forming an oxide over the silicon nitride layer, wherein the oxide and nitride layers and the nitridized layer form a composite dielectric; patterning and etching an opening in the composite dielectric to expose a portion of the substrate, wherein the composite dielectric can act as a mask barrier overlying the substrate during subsequent processing steps; forming a field oxide region in the opening, wherein the formation of the field oxide region densifies the oxide layer of the composite dielectric; patterning and etching the resulting composite dielectric to form a portion of an integrated circuit device.
Claim 20
Dependent Claim
13 words
The method of claim 16, wherein the oxide layer is formed by LPCVD.
Claim 21
Dependent Claim
20 words
The method of claim 16, wherein the oxide layer is formed at a temperature of approximately 800 to 1000° C.
Claim 22
Dependent Claim
20 words
The method claim 16, wherein the oxide layer is formed having a thickness of about 5 to about 50 angstroms.
Claim 23
Independent Claim
171 words
A method of forming a portion of a semiconductor integrated circuit; comprising the steps of: annealing a region of an upper surface of a substrate in an ambient comprising nitrogen forming a nitridized layer; forming a layer of silicon nitride over the nitridized layer; forming an oxide layer over the silicon nitride layer, wherein the oxide and nitride layers and the nitridized layer form a composite dielectric; forming a polysilicon layer over the composite dielectric; forming a nitride layer over the polysilicon layer; patterning and etching an opening in nitride and polysilicon layers and composite dielectric to expose a portion of the substrate, wherein the polysilicon layer and composite dielectric can act as a mask barrier overlying the substrate during subsequent processing steps; forming a field oxide region in the opening, wherein the formation of the field oxide region densifies the oxide layer of the composite dielectric; removing the nitride layer; and patterning and etching the polysilicon layer and resulting composite dielectric to form a portion of an integrated circuit device.
Claim 24
Independent Claim
171 words
A method of forming a portion of a semiconductor integrated circuit; comprising the steps of: annealing a region of an upper surface of a substrate in an ambient comprising nitrogen forming a nitridized layer; forming a layer of silicon nitride over the nitridized layer; forming an oxide layer over the silicon nitride layer, wherein the oxide and nitride layers and the nitridized layer form a composite dielectric; forming a polysilicon layer over the composite dielectric; forming a nitride layer over the polysilicon layer; patterning and etching an opening in nitride and polysilicon layers and composite dielectric to expose a portion of the substrate, wherein the polysilicon layer and composite dielectric can act as a mask barrier overlying the substrate during subsequent processing steps; forming a field oxide region in the opening, wherein the formation of the field oxide region densifies the oxide layer of the composite dielectric; removing the nitride layer; and patterning and etching the polysilicon layer and resulting composite dielectric to form a portion of an integrated circuit device.
Claim 25
Dependent Claim
37 words
The method of claim 20, wherein the polysilicon layer and composite dielectric are formed to a depth wherein an upper surface of the polysilicon layer is substantially planar with an upper surface of the field oxide region.
References Cited (Backward Citations)
US3520722A
Cited
US3745647A
Cited
US3861968A
Cited
US4026740A
Cited
US4160987A
Cited
US4101344A
Cited
US4553314A
Cited
US4553314B1
Cited
US4506437A
Cited
US4373248A
Cited
US4266985A
Cited
JPS5890778A
Cited
US4593453A
Cited
US4508757A
Cited
US4407696A
Cited
US4551910A
Cited
US4713356A
Cited
US4764248A
Cited
JPS63289820A
Cited
JPH01205553A
Cited
US5264724A
Cited
US5449640A
Cited
US5151381A
Cited
US5258643A
Cited
US5192707A
Cited
US5210056A
Cited
US5260229A
Cited
US5310692A
Cited
US5258333A
Cited
US5296411A
Cited
US5489790A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-07-26 | 2003-01-25 | 2003-07-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-07-26 | 2007-01-25 | 2007-07-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-07-26 | 2011-01-25 | 2011-07-27 | $7700.00 | Window Closed / Lapsed |