US4553314A
Expired / Lapsed
US
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Method for making a semiconductor device
Assignee: STMicroelectronics lnc USA
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Filing: 1982-09-30
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Granted: 1985-11-19
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Expires: 2002-09-30
Abstract
Abstract A method for making a semiconductor device is described in which overlapping polycrystalline silicon layers are deposited over selected portions of a semiconductor substrate and insulated from the substrate and from each other, thereby providing an improved semiconductor device for use in a random-access memory integrated circuit.
Inventors
- 👤 Tsiu C. Chan
- 👤 Chao Mai
- 👤 Myint Hswe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 07:41
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/35; G11C11/40; G11C11/401; G11C11/403; G11C11/404; G11C11/41; G11C11/412; H; H10; H10B; H10B12/00; H10B12/01; H10B12/30; H10D; H10D64/00; H10D64/01; H10D64/031; H10D64/037; H10P; H10P14/00; H10P14/60; H10P14/61; H10P76/00; H10P76/40; Y; Y10; Y10S; Y10S438/00; Y10S438/906
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
195 words
A method for making a portion of a semiconductor device comprising the steps of: (a) forming an oxide insulating layer on a surface of a semiconductor substrate, (b) forming a polysilicon layer on a selected portion of the oxide insulating layer, (c) selectively etching away portions of the oxide insulating layer using the polysilicon layer as a mask, thereby exposing a surface portion of the substrate previously covered by the oxide insulating layer, and thereby incidentally partially undercutting the polysilicon layer by lateral etching of portions of the oxide insulating layer under a peripheral edge of the polysilicon layer such that the depth of the undercutting is equal to or greater than the thickness of the oxide insulating layer, (d) diffusing dopants into the substrate through the exposed substrate portion, and (e) exposing the substrate to an oxidizing ambient simultaneously to oxidize both the peripheral edge of the polysilicon layer and the exposed substrate surface portion adjoining the lateral undercut region, such that the lateral undercut region is filled by a substrate oxide component and a peripheral edge polysilicon layer oxide component as both oxide components expand and grow in response to the oxidizing ambient.
Claim 2
Independent Claim
195 words
A method for making a portion of a semiconductor device comprising the steps of: (a) forming an oxide insulating layer on a surface of a semiconductor substrate, (b) forming a polysilicon layer on a selected portion of the oxide insulating layer, (c) selectively etching away portions of the oxide insulating layer using the polysilicon layer as a mask, thereby exposing a surface portion of the substrate previously covered by the oxide insulating layer, and thereby incidentally partially undercutting the polysilicon layer by lateral etching of portions of the oxide insulating layer under a peripheral edge of the polysilicon layer such that the depth of the undercutting is equal to or greater than the thickness of the oxide insulating layer, (d) diffusing dopants into the substrate through the exposed substrate portion, and (e) exposing the substrate to an oxidizing ambient simultaneously to oxidize both the peripheral edge of the polysilicon layer and the exposed substrate surface portion adjoining the lateral undercut region, such that the lateral undercut region is filled by a substrate oxide component and a peripheral edge polysilicon layer oxide component as both oxide components expand and grow in response to the oxidizing ambient.
Claim 3
Dependent Claim
22 words
The method of claim 1 further comprising the step (f) following step (e) of depositing a redundant oxide layer over the device.
Claim 4
Dependent Claim
32 words
The method of claim 1 wherein the polysilicon layer is diffused with dopants in step (d) simultaneously with the diffusion of dopants into the substrate, thereby making the polysilicon layer highly conductive.
Claim 5
Dependent Claim
16 words
The method of claim 1 wherein the polysilicon layer forms a gate of a memory cell.
Claim 6
Dependent Claim
16 words
The method of claim 1 wherein the polysilicon layer forms a gate of a field-effect transistor.
References Cited (Backward Citations)
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US3913211A
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-11-18 | 1989-05-20 | 1989-11-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-11-18 | 1993-05-20 | 1993-11-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-11-18 | 1997-05-20 | 1997-11-19 | $7700.00 | Window Closed / Lapsed |