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US4266985A Expired / Lapsed US ⏱️ 0.0 years remaining

Process for producing a semiconductor device including an ion implantation step in combination with direct thermal nitridation of the silicon substrate

Assignee: Fujitsu Ltd
•
Filing: 1979-05-18
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Granted: 1981-05-12
•
Expires: 1999-05-18
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Abstract

Abstract Impurity ions implanted into a semiconductor silicon substrate are not redistributed during a heating of the substrate from the substrate to the film. Such redistribution does not occur due to the direct nitridation of the silicon substrate for forming the silicon nitride film.

Inventors

  • 👤 Takashi Ito
  • 👤 Shinpei Hijiya

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-23 22:18
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/69; H10P14/694; H10P14/6943; H10P14/69433; H10D; H10D62/00; H10D62/10; H10D62/17; H10D62/213; H10D62/221; H10D62/235; H10D62/314; H10P14/63; H10P14/6302; H10P14/6316; H10P14/6322; H10P30/00; H10P30/20; H10P30/202; H10P30/204; H10P30/21; H10P30/212; H10P95/00; H10P95/90; Y; Y10; Y10S; Y10S148/00; Y10S148/112

Claims Analysis

Total Claims: 18
Claim 1
Independent Claim 81 words
A process for producing a semiconductor device comprising the steps of: forming a silicon nitride film by direct thermal nitridation of the silicon of a semiconductor silicon substrate; implanting impurity ions into said semiconductor silicon substrate, and; heating said semiconductor substrate to a temperature for electrically activating said impurities and for correcting damage to said semiconductor substrate caused by the ion implantation, while maintaining essentially the entire amount of the ion implanted impurities at the surface of said semiconductor silicon substrate.
Claim 2
Dependent Claim 81 words
A process for producing a semiconductor device comprising the steps of: forming a silicon nitride film by direct thermal nitridation of the silicon of a semiconductor silicon substrate; implanting impurity ions into said semiconductor silicon substrate, and; heating said semiconductor substrate to a temperature for electrically activating said impurities and for correcting damage to said semiconductor substrate caused by the ion implantation, while maintaining essentially the entire amount of the ion implanted impurities at the surface of said semiconductor silicon substrate.
Claim 3
Dependent Claim 17 words
A process according to claim 1, wherein said impurity ions are implanted through said silicon nitride film.
Claim 4
Dependent Claim 30 words
A process according to claim 2, wherein said impurity ions are implanted through a conductive material film deposited on said silicon nitride film and then through said silicon nitride film.
Claim 5
Dependent Claim 18 words
A process according to claim 1, wherein said impurity ions are implanted directly into said semiconductor silicon substrate.
Claim 6
Dependent Claim 28 words
A process according to claim 1, 2, 3 or 4, wherein the thickness of said silicon nitride film is in the range of from 20 to 100 angstroms.
Claim 7
Dependent Claim 23 words
A process according to claim 5, wherein the thickness of said silicon nitride is in the range of from 50 to 90 angstroms.
Claim 8
Dependent Claim 23 words
A process according to claim 2, wherein the ion energy of said impurities is in the range of from 10 to 400 KeV.
Claim 9
Dependent Claim 20 words
A process according to claim 7, wherein said ion energy is in the range of from 20 to 200 KeV.
Claim 10
Dependent Claim 203 words
A process for producing a semiconductor device comprising MISFET elements comprising the steps of: forming an insulation film on the surface of a semiconductor silicon substrate; selectively removing said insulation film and forming windows through said insulation film, thereby exposing surface portions for forming each of said MISFET elements; cleaning said exposed surface portions with an acid solution; forming a silicon nitride film by direct thermal nitridation of the silicon of said exposed surface portions of said semiconductor silicon substrate; implanting impurity ions into said semiconductor silicon substrate; heating said semiconductor substrate to a temperature for electrically activating said impurities and for correcting damage to said semiconductor substrate caused by the ion implantation, while maintaining essentially the entire amount of the ion implanted impurities at the surface of said semiconductor silicon substrate; depositing a conductive material film over said silicon nitride film; selectively removing said conductive material film and said silicon nitride film, and forming windows through these films, said windows exposing portions of the ion implanted surface of said semiconductor silicon substrate, and; diffusing impurities into said semiconductor silicon substrate, while maintaining essentially the entire amount of the ion implanted impurities at the semiconductor substrate surface below the remaining silicon nitride film.
Claim 11
Dependent Claim 203 words
A process for producing a semiconductor device comprising MISFET elements comprising the steps of: forming an insulation film on the surface of a semiconductor silicon substrate; selectively removing said insulation film and forming windows through said insulation film, thereby exposing surface portions for forming each of said MISFET elements; cleaning said exposed surface portions with an acid solution; forming a silicon nitride film by direct thermal nitridation of the silicon of said exposed surface portions of said semiconductor silicon substrate; implanting impurity ions into said semiconductor silicon substrate; heating said semiconductor substrate to a temperature for electrically activating said impurities and for correcting damage to said semiconductor substrate caused by the ion implantation, while maintaining essentially the entire amount of the ion implanted impurities at the surface of said semiconductor silicon substrate; depositing a conductive material film over said silicon nitride film; selectively removing said conductive material film and said silicon nitride film, and forming windows through these films, said windows exposing portions of the ion implanted surface of said semiconductor silicon substrate, and; diffusing impurities into said semiconductor silicon substrate, while maintaining essentially the entire amount of the ion implanted impurities at the semiconductor substrate surface below the remaining silicon nitride film.
Claim 12
Dependent Claim 17 words
A process according to claim 8, wherein said impurity ions are implanted through said silicon nitride film.
Claim 13
Dependent Claim 29 words
A process according to claim 10, wherein said impurity ions are implanted through a conductive material film deposited on said silicon nitride film and then said silicon nitride film.
Claim 14
Dependent Claim 18 words
A process according to claim 8, wherein said impurity ions are implanted directly into said semiconductor silicon substrate.
Claim 15
Dependent Claim 28 words
A process according to claim 9, 10, 11 or 12, wherein the thickness of said silicon nitride film is in the range of from 20 to 100 angstroms.
Claim 16
Dependent Claim 23 words
A process according to claim 13, wherein the thickness of said silicon nitride is in the range of from 50 to 90 angstroms.
Claim 17
Dependent Claim 27 words
A process according to claim 9, 10, 11 or 12, wherein the ion energy of said impurities is in the range of from 10 to 400 KeV.
Claim 18
Dependent Claim 20 words
A process according to claim 15, wherein said ion energy is in the range of from 20 to 200 KeV.

References Cited (Backward Citations)

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1984-05-11 1984-11-10 1985-05-12 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1988-05-11 1988-11-10 1989-05-12 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1992-05-11 1992-11-10 1993-05-12 $7700.00 Window Closed / Lapsed

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