US4170502A
Expired / Lapsed
US
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Method of manufacturing a gate turn-off thyristor
Assignee: Mitsubishi Electric Corp
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Filing: 1978-07-07
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Granted: 1979-10-09
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Expires: 1998-07-07
Abstract
Abstract This disclosure sets forth a method of manufacturing a gate turn-off (GTO) thyristor which includes the step of altering the lateral electrical resistance of one base region by out diffusion from selected portions of the base region.
Inventors
- 👤 Yaichiro Watakabe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 18:02
CPC Classifications
H; H10; H10P; H10P32/00; H10D; H10D18/00; H10D18/60; H10D62/00; H10D62/10; H10D62/17; H10D62/192; H10D62/206; Y; Y10; Y10S; Y10S148/00; Y10S148/114
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
232 words
A method of manufacturing a gate turn-off thyristor comprising forming a first region of a first-type of conductivity on a first major surface of a body of semiconductor material having a second type of conductivity by introducing doping means through said first surface, forming a second region of said first type of conductivity on a second major surface of said body of semiconductor material by introducing doping material through said second surface, said second region being doped to a higher level than said first region, said first and second major surfaces of said body of semiconductor material being substantially parallel to each other, forming a coating of a material on only predetermined portions of said second region, said coating being comprised of a material having a lower oxidation rate than said semiconductor material and being impervious to the diffusion of atoms of the doping material used to form said second region, heating said body of semiconductor material to form an oxide coating on that portion of said second region not having a coating of said material thereon and to out diffuse doping material from the portions of said second region not having the coating of said material thereon, forming a third region in a predetermined portion of said second region, said third region having said second type of semiconductivity and affixing metal electrodes to said first region, second region and third region.
Claim 2
Independent Claim
232 words
A method of manufacturing a gate turn-off thyristor comprising forming a first region of a first-type of conductivity on a first major surface of a body of semiconductor material having a second type of conductivity by introducing doping means through said first surface, forming a second region of said first type of conductivity on a second major surface of said body of semiconductor material by introducing doping material through said second surface, said second region being doped to a higher level than said first region, said first and second major surfaces of said body of semiconductor material being substantially parallel to each other, forming a coating of a material on only predetermined portions of said second region, said coating being comprised of a material having a lower oxidation rate than said semiconductor material and being impervious to the diffusion of atoms of the doping material used to form said second region, heating said body of semiconductor material to form an oxide coating on that portion of said second region not having a coating of said material thereon and to out diffuse doping material from the portions of said second region not having the coating of said material thereon, forming a third region in a predetermined portion of said second region, said third region having said second type of semiconductivity and affixing metal electrodes to said first region, second region and third region.
Claim 3
Dependent Claim
23 words
The method of claim 1 in which said coating formed on predetermined portions of said second region is Si 3 N 4 .
Claim 4
Dependent Claim
41 words
The method of claim 1 in which said coating formed on predetermined portions of said second region consists of a first layer of SiO 2 and a second layer of Si 3 N 4 over said layer of SiO 2 .
Claim 5
Dependent Claim
39 words
The method of claim 1 in which said first and said second regions are of a P+ type conductivity and said body of semiconductor material is of N type conductivity and said third region is of N+ type conductivity.
Claim 6
Dependent Claim
38 words
The method of claim 4 in which at least the second region is formed by doping with boron and the formation of said oxide coating is effected by heating in wet oxygen at 1,100° C. for one hour.
Claim 7
Independent Claim
175 words
A method of manufacturing a gate turn-off thyristor comprising forming a first P- type conductivity emitter region on a first major surface of a body of N-- type conductivity semiconductor material, forming a second region of P+ type conductivity on a second major surface of said body of N- type conductivity semiconductor material, said first and second major surfaces of said body of semiconductor material being substantially parallel to each other, forming a coating of Si 3 N 4 on predetermined portions of said second region, heating said body of semiconductor to form an oxide coating of that portion of said second region of P+ type conductivity not having the coating of Si 3 N 4 thereon, and to out diffuse a portion of the doping material from the portions of said second region of P+ type conductivity not having the coating of Si 3 N 4 thereon, forming a N+ type conductivity emitter region in a predetermined portion of said second region, and affixing metal electrical contacts to said first, second and third regions.
Claim 8
Independent Claim
175 words
A method of manufacturing a gate turn-off thyristor comprising forming a first P- type conductivity emitter region on a first major surface of a body of N-- type conductivity semiconductor material, forming a second region of P+ type conductivity on a second major surface of said body of N- type conductivity semiconductor material, said first and second major surfaces of said body of semiconductor material being substantially parallel to each other, forming a coating of Si 3 N 4 on predetermined portions of said second region, heating said body of semiconductor to form an oxide coating of that portion of said second region of P+ type conductivity not having the coating of Si 3 N 4 thereon, and to out diffuse a portion of the doping material from the portions of said second region of P+ type conductivity not having the coating of Si 3 N 4 thereon, forming a N+ type conductivity emitter region in a predetermined portion of said second region, and affixing metal electrical contacts to said first, second and third regions.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-10-08 | 1983-04-09 | 1983-10-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-10-08 | 1987-04-09 | 1987-10-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-10-08 | 1991-04-09 | 1991-10-09 | $7700.00 | Window Closed / Lapsed |