Control of diffusion profiles in a thyristor by a grown oxide layer

Claim 1

THE PROCESS OF FORMING A PLURALITY OF SPACED P-N JUNCTIONS IN A MONOCRYSTALLINE SILICON WAFER, SAID PROCESS COMPRISING THE STEPS OF: FORMING A DIFFUSION ON THE OUTER SURFACE OF SAID SILICON WAFER, FORMING AT LEAST ONE WINDOW IN SAID MASK, LOADING SAID WAFER INTO A DIFFUSION FURNACE AND LOADING A MEASURED MASS OF A GROUP III-V INTERMETALLIC COMPOUND AND A MEASURED MASS OF A PURE METAL SELECTED FROM THE GROUP CONSISTING OF GROUP III AND GROUP V METALS INTO SAID DIFFUSION FURNACE, HEATING SAID DIFFUSION FURNACE TO A DIFFUSION TEMPERATURE AND FORMING, IN A SINGLE DIFFUSION CYCLE, A P-TYPE REGION IN SAID WAFER BENEATH SAID DIFFUSION MASK AND AN N-TYPE REGION IN REGIONS OF SAID WAFER EXPOSED TO SAID MASK WITH THE JUNCTION BETWEEN SAID P-TYPE AND N-TYPE REGIONS EXTENDING TO AND TERMINATING ON SAID OUTER SURFACE OF SAID WAFER AND THEREAFTER STRIPPING AND REDEPOSITING AN OXIDE COARING OVER THE ENTIRE WAFER, AND RAISING THE TEMPERATURE OF SAID WAFER, THEREBY TO VARY THE IMPURITY CONCENTRATION OF BOTH GROUP III AND V IMPURITIES WITHIN THE WAFER.