Method of making a semiconductor device

Claim 1

A method of fabricating a semiconductor device having a multilayer interconnection structure, the method comprising: forming a first insulation layer on a semiconductor substrate; forming an etching prevention film on said first insulation layer; forming a first opening through the etching prevention film and through the first insulation layer; forming a first interconnection layer in said first opening; forming a second insulation layer on said etching prevention film and said first interconnection layer integrally without interposing any etching prevention film therein; forming a hole of a pattern identical with a second opening to be formed later in said second insulation layer from an upper surface of the second insulation layer to a depth by etching; forming said second opening for a via hole reaching the upper surface of said first interconnection layer and a third opening having a diameter larger than that of said second opening and being continuous with said second opening in said second insulation layer, by etching a region of said second insulation layer containing the pattern identical with said second opening so as to make the bottom of the hole of the pattern identical with said second opening reach the upper surface of said first interconnection layer; and forming a second interconnection layer in said second and third openings so that the bottom of said second interconnection layer directly contacts the upper surface of said first interconnection layer.

Claim 2

A method of fabricating a semiconductor device having a multilayer interconnection structure, the method comprising: forming a first insulation layer on a semiconductor substrate; forming an etching prevention film on said first insulation layer; forming a first opening through the etching prevention film and through the first insulation layer; forming a first interconnection layer in said first opening; forming a second insulation layer on said etching prevention film and said first interconnection layer integrally without interposing any etching prevention film therein; forming a hole of a pattern identical with a second opening to be formed later in said second insulation layer from an upper surface of the second insulation layer to a depth by etching; forming said second opening for a via hole reaching the upper surface of said first interconnection layer and a third opening having a diameter larger than that of said second opening and being continuous with said second opening in said second insulation layer, by etching a region of said second insulation layer containing the pattern identical with said second opening so as to make the bottom of the hole of the pattern identical with said second opening reach the upper surface of said first interconnection layer; and forming a second interconnection layer in said second and third openings so that the bottom of said second interconnection layer directly contacts the upper surface of said first interconnection layer.