Semiconductor processing method of forming an electrical interconnection between an outer layer and an inner layer

Claim 1

A semiconductor processing method of forming an electrical interconnection between a base region and an outer layer comprising the following steps: providing a substrate having a base region to which electrical connection is to be made; providing a first layer of an electrically conductive first material over the substrate to a first thickness; providing an etch stop layer over the first layer, the etch stop layer comprising a material to which the first material is selectively etchable; etching a contact opening through the etch stop layer and first layer to the base region, the contact opening defining a contact opening upper edge of the first layer; providing a second layer of the first material outwardly of the etch stop layer and within the contact opening to a second thickness, the second thickness being greater than the first thickness and the second layer extending outwardly beyond the first layer contact opening upper edge; removing first material of the second layer and defining a second layer plug within the contact opening, the second layer plug having an outermost surface extending outwardly beyond the first layer contact opening upper edge and thereby providing the second layer plug to be of greater thickness than the first layer; masking outwardly of the first layer and the second layer plug to define a common mask pattern for definition of an electrically conductive circuit component from the first layer which connects with the base region through the second layer plug; and etching unmasked portions of the first layer and the second layer plug using the common mask to define an electrically conductive circuit component which connects with the base region through the second layer plug, the greater thickness of the second layer plug as compared to the thickness of the first layer restricting etching into the base region during etching.