Process for etching and depositing integrated circuit interconnections and contacts

Claim 1

A process for producing an integrated circuit stage having a dielectric layer covering interconnection lines and connection points linking the interconnection lines to conductive portions of the integrated circuit positioned below the dielectric layer, the latter having a lower sublayer covering the connection points and an upper sublayer covering the interconnection lines, said process comprising the following steps in sequence of: depositing the dielectric layer; at least partially etching the dielectric layer at the locations of the connection points after producing a first mask on the dielectric layer; final etching of the dielectric layer at the locations of the connection points and the upper sublayer at the locations of the interconnection lines after producing a second mask on the dielectric layer; once depositing a conductive material on the dielectric layer, so as to: (i) fill the etched portions to contemporaneously form the connection points and interconnection lines, and (ii) produce an upper conductive layer above the dielectric layer, said upper conductive layer forming a planar upper surface, said conductive material being suitable for formation of said planar surface; and, eliminating the conductive material above the dielectric layer to form a final planar layer comprising the interconnection lines and the dielectric.