US5006484A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Making a semiconductor device with contact holes having different depths
Assignee: Oki Electric Industry Co Ltd
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Filing: 1990-01-31
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Granted: 1991-04-09
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Expires: 2010-01-31
Abstract
Abstract In a process of fabrication of a semiconductor device having a relatively deep contact hole and a relatively shallow contact hole; a lower interlayer insulating layer is formed on a semiconductor substrate, and then subjected to heat treatment to flow; an upper interlayer insulating film is then formed on the lower interlayer insulating film, and is then subjected to heat treatment to flow; a non-flowing film which does not flow is then formed in the area where the shallow contact hole will be formed; and the deep and the shallow holes are then formed through the upper interlayer insulating film and the non-flowing film and heat treatment is conducted to cause flow of the upper interlayer insulating film whereby the flow of the upper interlayer insulating layer occurs except at the area covered by the non-flowing film. The deep and the shallow contact holes are then filled with metal by selective CVD; and an interconnection is then formed to have contact with the metal filling the contact holes.
Inventors
- 👤 Yusuke Harada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 15:53
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/011; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/081; Y; Y10; Y10S; Y10S148/00; Y10S148/133; Y10S438/00; Y10S438/97
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
201 words
A process for fabrication a semiconductor device having a relatively deep contact hole and a relatively shallow contact hole, comprising the steps of: (a) forming a lower interlayer insulating film having a flowing property on a semiconductor substrate: (b) performing a heat treatment to cause said lower interlayer insulating film to flow: (c) forming an upper interlayer insulating film having a flowing property on said lower interlayer insulating film; (d) performing a heat treatment to cause said upper interlayer insulating film to flow; (e) forming a non-flowing film which does not have a flowing property in the area within which said shallow contact hole will be formed; (f) forming said deep contact hole through said upper interlayer insulating film and said lower interlayer insulating film and forming said shallow contact hole through said upper interlayer insulating film and said non-flowing film; (g) performing a heat treatment to cause said upper interlayer insulating film to flow, whereby said upper interlayer insulating layer flows except at the area covered by said non-flowing film; (h) filling said deep contact hole and said shallow contact hole with metal by selective CVD; and (i) forming an interconnect in contact with said metal filling said contact holes.
Claim 2
Dependent Claim
201 words
A process for fabrication a semiconductor device having a relatively deep contact hole and a relatively shallow contact hole, comprising the steps of: (a) forming a lower interlayer insulating film having a flowing property on a semiconductor substrate: (b) performing a heat treatment to cause said lower interlayer insulating film to flow: (c) forming an upper interlayer insulating film having a flowing property on said lower interlayer insulating film; (d) performing a heat treatment to cause said upper interlayer insulating film to flow; (e) forming a non-flowing film which does not have a flowing property in the area within which said shallow contact hole will be formed; (f) forming said deep contact hole through said upper interlayer insulating film and said lower interlayer insulating film and forming said shallow contact hole through said upper interlayer insulating film and said non-flowing film; (g) performing a heat treatment to cause said upper interlayer insulating film to flow, whereby said upper interlayer insulating layer flows except at the area covered by said non-flowing film; (h) filling said deep contact hole and said shallow contact hole with metal by selective CVD; and (i) forming an interconnect in contact with said metal filling said contact holes.
Claim 3
Dependent Claim
31 words
The process of claim 1, further comprising the step of: (j) forming an additional interconnection on said lower interlayer insulating layer; before said step of forming an upper interlayer insulating layer.
Claim 4
Dependent Claim
30 words
The process of claim 1, further comprising the step of: (k) forming an intermediate insulating film over said additional interconnection, before said step of forming an upper interlayer insulating layer.
Claim 5
Dependent Claim
16 words
The process of claim 2, wherein said additional interconnection is an interconnection for a gate electrode.
Claim 6
Dependent Claim
17 words
The process of claim 3, wherein said intermediate interlayer insulating layer does not have a flowing property.
Claim 7
Dependent Claim
16 words
The process of claim 5, wherein said intermediate insulating film is formed of SiO 2 .
Claim 8
Dependent Claim
15 words
The process of claim 1, wherein said lower interlayer insulating layer is formed of BPSG.
Claim 9
Dependent Claim
15 words
The process of claim 1, wherein said upper interlayer insulating layer is formed of BPSG.
Claim 10
Dependent Claim
13 words
The process of claim 1, wherein said non-flowing film is an insulating film.
Claim 11
Dependent Claim
15 words
The process of claim 1, wherein said non-flowing film is formed of Sio 2 .
Claim 12
Dependent Claim
23 words
The process of claim 1, wherein said non-flowing film is not formed in the area where the deep contact hole will be formed.
Claim 13
Dependent Claim
18 words
The process of claim 4, wherein said shallow contact hole is formed for contact with said additional interconnection.
Claim 14
Dependent Claim
167 words
A process of forming an integrated circuit structure having first and second contact holes, said first hole being shallower than said second hole, comprising the steps of: forming a multi-layar structure above a substrate, the multilayer structure comprising a lower insulating layer having a substantially flat upper surface, and a flowable upper insulating layer above said flat upper surface; establishing a non-flowing film upon said upper insulating layer where the first contact hole is to be formed while leaving the region where the second contact hole is to be formed not covered by said non-flowing film; then forming said first contact hole through said non-flowing film and forming said second contact hole, said first hole being formed shallower than said second hole; then flowing said upper insulating film while protecting the region surrounding said first contact hole by said non-flowing film; then filling said first and second contact holes at least partially with a conductive material; and then forming interconnections to said first and second contact holes.
Claim 15
Dependent Claim
167 words
A process of forming an integrated circuit structure having first and second contact holes, said first hole being shallower than said second hole, comprising the steps of: forming a multi-layar structure above a substrate, the multilayer structure comprising a lower insulating layer having a substantially flat upper surface, and a flowable upper insulating layer above said flat upper surface; establishing a non-flowing film upon said upper insulating layer where the first contact hole is to be formed while leaving the region where the second contact hole is to be formed not covered by said non-flowing film; then forming said first contact hole through said non-flowing film and forming said second contact hole, said first hole being formed shallower than said second hole; then flowing said upper insulating film while protecting the region surrounding said first contact hole by said non-flowing film; then filling said first and second contact holes at least partially with a conductive material; and then forming interconnections to said first and second contact holes.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-04-08 | 1994-10-08 | 1995-04-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-04-08 | 1998-10-08 | 1999-04-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-04-08 | 2002-10-08 | 2003-04-09 | $7700.00 | Window Closed / Lapsed |