Patent US5915977A successfully refreshed from Google Patents.
US5915977A
Expired / Lapsed
US
⏱️ 0.0 years remaining
System and interconnect for making temporary electrical connections with bumped semiconductor components
Assignee: Micron Technology Inc
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Filing: 1998-08-24
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Granted: 1999-06-29
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Expires: 2018-08-24
Abstract
Abstract An interconnect and system for establishing temporary electrical communication with semiconductor components having contact bumps are provided. The interconnect includes a substrate with patterns of contact members adapted to electrically contact the contact bumps. The substrate can be formed of a material such as ceramic, silicon, FR-4, or photo-chemically machineable glass. The contact members can be formed as recesses covered with conductive layers in electrical communication with conductors and terminal contacts on the substrate. Alternately, the contact members can be formed as projections adapted to penetrate the contact bumps, as microbumps with a rough textured surface, or as a deposited layer formed with recesses. The interconnect can be employed in a wafer level test system for testing dice contained on a wafer, or in a die level test system for testing bare bumped dice or bumped chip scale packages.
Inventors
- 👤 David R. Hembree
- 👤 John O. Jacobson
- 👤 James M. Wark
- 👤 Warren M. Farnworth
- 👤 Salman Akram
- 👤 Alan G. Wood
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 11:03
CPC Classifications
H; H10; H10P; H10P72/00; H10P72/04; H10P72/0446; G; G01; G01R; G01R1/00; G01R1/02; G01R1/04; G01R1/0408; H05; H05K; H05K3/00; H05K3/30; H05K3/32; H05K3/325; H05K3/326; H10W; H10W72/00; H10W72/071; H10W72/072; H10W72/07221; H10W72/07227; H10W72/07251; H10W72/07252; H10W72/20; H10W72/221; H10W72/241; H10W90/00; H10W90/701; H10W90/721; H10W90/724
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
110 words
A system for testing a semiconductor component comprising: a testing apparatus comprising an electrical connector in electrical communication with testing circuitry; an interconnect on the testing apparatus comprising: a substrate; a compliant layer on the substrate; a contact member on the substrate comprising a conductive layer on the compliant layer, and a recess in the conductive layer configured to retain a contact bump on the component, the conductive layer having a peripheral edge configured to penetrate a surface of the contact bump to form a peripheral groove therein; and a contact on the substrate in electrical communication with the conductive layer and configured for electrical communication with the electrical connector.
Claim 2
Independent Claim
110 words
A system for testing a semiconductor component comprising: a testing apparatus comprising an electrical connector in electrical communication with testing circuitry; an interconnect on the testing apparatus comprising: a substrate; a compliant layer on the substrate; a contact member on the substrate comprising a conductive layer on the compliant layer, and a recess in the conductive layer configured to retain a contact bump on the component, the conductive layer having a peripheral edge configured to penetrate a surface of the contact bump to form a peripheral groove therein; and a contact on the substrate in electrical communication with the conductive layer and configured for electrical communication with the electrical connector.
Claim 3
Dependent Claim
20 words
The system of claim 1 wherein the compliant layer comprises an elastomeric material deposited in a pit in the substrate.
Claim 4
Dependent Claim
15 words
The system of claim 1 wherein the system comprises a temporary package for the component.
Claim 5
Dependent Claim
14 words
The system of claim 1 wherein the testing apparatus comprises a wafer probe handler.
Claim 6
Independent Claim
139 words
A system for testing a semiconductor component comprising: a testing apparatus comprising a plurality of electrical connectors in electrical communication with testing circuitry; an interconnect mounted to the testing apparatus comprising a plurality of contact members formed on a surface thereof, each contact member comprising a stepped recess configured to retain and electrically engage a contact bump on the component, the recess comprising a conductive layer with a first peripheral edge proximate to the surface configured to penetrate and electrically contact the contact bump to form a first peripheral groove therein, and a second peripheral edge within the recess configured to penetrate and electrically contact the contact bump to form a second peripheral groove therein; and a plurality of contacts on the interconnect in electrical communication with the contact members and configured for electrical communication with the electrical connectors.
Claim 7
Independent Claim
139 words
A system for testing a semiconductor component comprising: a testing apparatus comprising a plurality of electrical connectors in electrical communication with testing circuitry; an interconnect mounted to the testing apparatus comprising a plurality of contact members formed on a surface thereof, each contact member comprising a stepped recess configured to retain and electrically engage a contact bump on the component, the recess comprising a conductive layer with a first peripheral edge proximate to the surface configured to penetrate and electrically contact the contact bump to form a first peripheral groove therein, and a second peripheral edge within the recess configured to penetrate and electrically contact the contact bump to form a second peripheral groove therein; and a plurality of contacts on the interconnect in electrical communication with the contact members and configured for electrical communication with the electrical connectors.
Claim 8
Dependent Claim
19 words
The system of claim 5 wherein the component comprises a wafer and the testing apparatus comprises a wafer handler.
Claim 9
Dependent Claim
24 words
The system of claim 5 wherein the component comprises a bare die or a chip scale package and the system comprises a temporary package.
Claim 10
Dependent Claim
23 words
The system of claim 5 further comprising a compressible member on the interconnect for cushioning a contact force applied by the testing apparatus.
Claim 11
Dependent Claim
20 words
The system of claim 5 wherein the recess is configured to allow the contact bums to deform into the recess.
Claim 12
Dependent Claim
35 words
The system of claim 5 wherein a diameter of the first peripheral edge is selected to electrically contact a first contact bump having a first diameter or a second contact bump having a second diameter.
Claim 13
Dependent Claim
27 words
The system of claim 5 wherein the contact members are configured to electrically engage a plurality of contact bumps on the component in a ball grid array.
Claim 14
Independent Claim
127 words
A system for testing a semiconductor component comprising: a testing apparatus comprising a plurality of electrical connectors in electrical communication with testing circuitry; an interconnect on the testing apparatus comprising a plurality of spaced arrays of contact members configured to electrically engage a plurality of contact bumps formed in a grid array on the component, each spaced array comprising a plurality of projections configured to retain a contact bump on the component in a space therebetween, each projection at least partially covered with a conductive layer having an edge configured to penetrate and electrically contact the contact bump and to form an elongated groove in a surface thereof; a plurality of contacts on the interconnect in electrical communication with the contact members and with the electrical connectors.
Claim 15
Independent Claim
127 words
A system for testing a semiconductor component comprising: a testing apparatus comprising a plurality of electrical connectors in electrical communication with testing circuitry; an interconnect on the testing apparatus comprising a plurality of spaced arrays of contact members configured to electrically engage a plurality of contact bumps formed in a grid array on the component, each spaced array comprising a plurality of projections configured to retain a contact bump on the component in a space therebetween, each projection at least partially covered with a conductive layer having an edge configured to penetrate and electrically contact the contact bump and to form an elongated groove in a surface thereof; a plurality of contacts on the interconnect in electrical communication with the contact members and with the electrical connectors.
Claim 16
Dependent Claim
14 words
The system of claim 12 wherein each contact member comprises at least two projections.
Claim 17
Dependent Claim
20 words
The system of claim 11 wherein the component comprises a wafer and the testing apparatus comprises a wafer probe handler.
Claim 18
Dependent Claim
26 words
The system of claim 11 wherein the component comprises a chip scale package and the system comprises a temporary package for housing the chip scale package.
Claim 19
Independent Claim
134 words
A system for testing a semiconductor component comprising: a testing apparatus comprising an electrical connector in electrical communication with testing circuitry; an interconnect on the testing apparatus configured to establish electrical communication between the testing circuitry and the component; the interconnect comprising: a substrate; a compliant layer on the substrate; a contact member comprising a conductive layer on the compliant layer and a recess in the conductive layer having a peripheral edge configured to penetrate a contact bump on the component, with a diameter of the edge and a depth of the recess selected to electrically engage a first contact bump having a minimum average diameter, or a second contact bump having a maximum average diameter; and a contact on the interconnect in electrical communication with the conductive layer and with the electrical connector.
Claim 20
Independent Claim
134 words
A system for testing a semiconductor component comprising: a testing apparatus comprising an electrical connector in electrical communication with testing circuitry; an interconnect on the testing apparatus configured to establish electrical communication between the testing circuitry and the component; the interconnect comprising: a substrate; a compliant layer on the substrate; a contact member comprising a conductive layer on the compliant layer and a recess in the conductive layer having a peripheral edge configured to penetrate a contact bump on the component, with a diameter of the edge and a depth of the recess selected to electrically engage a first contact bump having a minimum average diameter, or a second contact bump having a maximum average diameter; and a contact on the interconnect in electrical communication with the conductive layer and with the electrical connector.
Claim 21
Dependent Claim
31 words
The system of claim 16 wherein the recess comprises a stepped member having a first peripheral edge proximate a surface of the substrate and a second peripheral edge within the recess.
Claim 22
Dependent Claim
23 words
The system of claim 16 wherein the substrate comprises a pit and the compliant layer comprises an elastomeric material deposited in the pit.
Claim 23
Dependent Claim
25 words
The system of claim 16 wherein the component comprises a chip scale package and the system comprises a temporary package for the chip scale package.
Claim 24
Independent Claim
136 words
A system for testing a semiconductor component comprising: a testing apparatus comprising an electrical connector in electrical communication with testing circuitry; an interconnect on the testing apparatus configured to establish electrical communication between the testing circuitry and the component; the interconnect comprising: a substrate; an elastomeric compliant layer on the substrate; a contact member on the substrate configured to electrically contact a contact bump on the component, the contact member comprising a conductive layer on the compliant layer and a recess in the conductive layer configured to retain the contact bump, the recess and conductive layer forming a peripheral edge configured to penetrate a surface of the contact bump to form a groove therein; and a contact on the substrate in electrical communication with the conductive layer and configured for electrical communication with the electrical connector.
Claim 25
Independent Claim
136 words
A system for testing a semiconductor component comprising: a testing apparatus comprising an electrical connector in electrical communication with testing circuitry; an interconnect on the testing apparatus configured to establish electrical communication between the testing circuitry and the component; the interconnect comprising: a substrate; an elastomeric compliant layer on the substrate; a contact member on the substrate configured to electrically contact a contact bump on the component, the contact member comprising a conductive layer on the compliant layer and a recess in the conductive layer configured to retain the contact bump, the recess and conductive layer forming a peripheral edge configured to penetrate a surface of the contact bump to form a groove therein; and a contact on the substrate in electrical communication with the conductive layer and configured for electrical communication with the electrical connector.
Claim 26
Dependent Claim
18 words
The system of claim 20 wherein the elastomeric material comprises silicone deposited in a pit on the substrate.
Claim 27
Dependent Claim
17 words
The system of claim 20 the recess comprises a stepped member having at least two peripheral edges.
Claim 28
Dependent Claim
28 words
The system of claim 20 wherein the component comprises a plurality of contact bumps in a ball grid array and the interconnect comprises a plurality of contact members.
Claim 29
Dependent Claim
17 words
The system of claim 20 wherein the component comprise a bare die or a chip scale package.
References Cited (Backward Citations)
US4937653A
Cited
US5072289A
Cited
US5006792A
Cited
US4969828A
Cited
US5088190A
Cited
US5172050A
Cited
US5495179A
Cited
US5607818A
Cited
US5815000A
Cited
US5716218A
Cited
US5408190A
Cited
US5541525A
Cited
US5519332A
Cited
US5440240A
Cited
US5487999A
Cited
US5206585A
Cited
US5289631A
Cited
US5481205A
Cited
US5477160A
Cited
US5534785A
Cited
US5453701A
Cited
US5329423A
Cited
US5420520A
Cited
US5523696A
Cited
US5414372A
Cited
US5517125A
Cited
US5530376A
Cited
US5543725A
Cited
US5326428A
Cited
US5483741A
Cited
US5592736A
Cited
US5500605A
Cited
US5625298A
Cited
US5581195A
Cited
US5451165A
Cited
US5691041A
Cited
US5789271A
Cited
US5869974A
Cited
US5808360A
Cited
US5834366A
Cited
US5783461A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-06-28 | 2002-12-28 | 2003-06-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-06-28 | 2006-12-28 | 2007-06-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-06-28 | 2010-12-28 | 2011-06-29 | $7700.00 | Window Closed / Lapsed |