US5848467A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Methods of making semiconductor chip assemblies
Assignee: Adeia Semiconductor Solutions LLC
•
Filing: 1997-05-13
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Granted: 1998-12-15
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Expires: 2017-05-13
Abstract
Abstract Semiconductor chip assemblies are fabricated by providing a wafer having a plurality of semiconductor chips and providing a sheet separate from the wafer having a plurality of dielectric elements. Each chip has a plurality of contacts and each dielectric element has a plurality of terminal formed thereon. The sheet and the wafer are then assembled so that the terminals on the dielectric elements face away from the wafer and so that each chip is associated with a dielectric element. The contacts on each chip are connected to the terminals on a dielectric element associated with the chip. The individual dialectic elements are then severed from the sheet and the individual chips are severed from the wafer after the assembling and connecting step to provide subassemblies, each subassembly including a chip and the dielectric element associated with the chip. In another embodiment, a plurality of individual dielectric elements separate from one another and separate from a wafer are provided.
Inventors
- 👤 Igor Y. Khandros
- 👤 Thomas H. DiStefano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 00:59
CPC Classifications
H; H10; H10P; H10P72/00; H10P72/70; H10P72/74; H10P72/7402; H10D; H10D84/00; H10D84/01; H10D84/02; H10D84/03; H10D84/038; H10P74/00; H10P74/27; H10P74/273; H10W; H10W70/00; H10W70/40; H10W70/479; H10W70/60; H10W70/62; H10W70/63; H10W70/635; H10W70/65; H10W70/657; H10W70/67; H10W70/68; H10W70/688; H10W74/00; H10W74/10; H10W74/111; H10W74/131; H10W74/144; H10W90/00; H10P72/7416; H10W72/00; H10W72/01; H10W72/013; H10W72/01331; H10W72/071; H10W72/072; H10W72/07231; H10W72/07236; H10W72/50; H10W72/541; H10W72/547; H10W72/5473; H10W72/60; H10W72/851; H10W72/874; H10W72/884; H10W72/90; H10W72/941; H10W72/9413; H10W90/20; H10W90/284; H10W90/701; H10W90/721; H10W90/722; H10W90/724; H10W90/751; H10W90/754; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/49128; Y10T29/4913; Y10T29/49144; Y10T29/49146; Y10T29/49147; Y10T29/49169; Y10T29/49171
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
136 words
A method of making a plurality of semiconductor chip assemblies comprising the steps of: (a) providing a semicondutor wafer including a plurality of semiconductor chips having contacts thereon; (b) providing a sheet separate from said wafer incorporating a plurality of dielectric elements having terminals thereon, (c) assembling the sheet to the wafer so that the terminals on said dielectic elements face away from the wafer and so that said chips are associated with said dielectric elements, and connecting contacts on said chips to terminals on the dielectric elements associated with said chips; and (d) severing the individual dielectric elements from the sheet and severing the individual chips from said wafer after said assembling and connecting step so as to provide a plurality of subassemblies, each said subassembly including a chip and a dielectric element associated therewith.
Claim 2
Independent Claim
136 words
A method of making a plurality of semiconductor chip assemblies comprising the steps of: (a) providing a semicondutor wafer including a plurality of semiconductor chips having contacts thereon; (b) providing a sheet separate from said wafer incorporating a plurality of dielectric elements having terminals thereon, (c) assembling the sheet to the wafer so that the terminals on said dielectic elements face away from the wafer and so that said chips are associated with said dielectric elements, and connecting contacts on said chips to terminals on the dielectric elements associated with said chips; and (d) severing the individual dielectric elements from the sheet and severing the individual chips from said wafer after said assembling and connecting step so as to provide a plurality of subassemblies, each said subassembly including a chip and a dielectric element associated therewith.
Claim 3
Dependent Claim
29 words
A method as claimed in claim 1 further comprising the step of encapsulating connections between said terminals and said contacts with a dielectric encapsulant prior to said severing step.
Claim 4
Dependent Claim
41 words
A method as claimed in claim 2 wherein said encapsulating step includes the step of applying said encapsulant so that the encapsulant penetrates between the dielectric elements and the chips to form a layer between the dielectric elements and the chips.
Claim 5
Dependent Claim
14 words
A method as claimed in claim 2 wherein said encapsulant is a compliant material.
Claim 6
Independent Claim
132 words
A method of making a plurality of semiconductor chip assemblies comprising the steps of: (a) providing a semicondutor wafer including a plurality of semiconductor chips having contacts thereon; (b) providing a plurality of individual dielectric elements separate from one another and separate from said wafer, said dielectric elements having terminals thereon; (c) assembling said dielectric elements to the wafer so that the terminals on said dielectic elements face away from the wafer and so that said chips are associated with said dielectric elements, and connecting contacts on said chips to terminals on the dielectric elements associated with said chips; and (d) severing the individual chips from said wafer after said assembling and connecting step so as to provide a plurality of subassemblies, each including a chip and a dielectric element associated therewith.
Claim 7
Independent Claim
132 words
A method of making a plurality of semiconductor chip assemblies comprising the steps of: (a) providing a semicondutor wafer including a plurality of semiconductor chips having contacts thereon; (b) providing a plurality of individual dielectric elements separate from one another and separate from said wafer, said dielectric elements having terminals thereon; (c) assembling said dielectric elements to the wafer so that the terminals on said dielectic elements face away from the wafer and so that said chips are associated with said dielectric elements, and connecting contacts on said chips to terminals on the dielectric elements associated with said chips; and (d) severing the individual chips from said wafer after said assembling and connecting step so as to provide a plurality of subassemblies, each including a chip and a dielectric element associated therewith.
Claim 8
Dependent Claim
29 words
A method as claimed in claim 5 further comprising the step of encapsulating connections between said terminals and said contacts with a dielectric encapsulant prior to said severing step.
Claim 9
Dependent Claim
41 words
A method as claimed in claim 6 wherein said encapsulating step includes the step of applying said encapsulant so that the encapsulant penetrates between the dielectric elements and the chips to form a layer between the dielectric elements and the chips.
Claim 10
Dependent Claim
14 words
A method as claimed in claim 6 wherein said encapsulant is a compliant material.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-12-14 | 2002-06-15 | 2002-12-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-12-14 | 2006-06-15 | 2006-12-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-12-14 | 2010-06-15 | 2010-12-15 | $7700.00 | Window Closed / Lapsed |