Patent US5848018A successfully refreshed from Google Patents.
US5848018A
Expired / Lapsed
US
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Memory-row selector having a test function
Assignee: STMicroelectronics lnc USA
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Filing: 1997-09-10
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Granted: 1998-12-08
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Expires: 2017-09-10
Abstract
Abstract A memory-row selector includes an address input terminal, a mode terminal, and even-row-select and odd-row-select terminals. While a test signal level occupies the mode terminal (ie., during a test mode), the selector places either an active level or an inactive level on both of the even-row-select and odd-row-select terminals. An active level on both of the select terminals enables both even-row and odd-row word lines, and allows writing to or reading from memory cells in both odd and even rows. An inactive level on both of the select terminals disables both even-row and odd-row word lines, including the word line coupled to the addressed memory cell.
Inventors
- 👤 David C. McClure
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 09:19
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/30; G11C29/34; G11C8/00; G11C8/12
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
157 words
A memory device, comprising: an address decoder; an array of memory cells arranged in rows and columns, each column having a bit-true and a bit-complement lines coupled to those of said memory cells in said each column, each row having a word line coupled to those of said memory cells in said each row; a read/write circuit coupled to said decoder and to said array, said read/write circuit operable to simultaneously drive first and second test signals respectively onto said bit-true and bit-complement lines of an addressed column during testing of said addressed column; and a memory-row selector coupled to said address decoder and to said array, said selector having an even-row output terminal and an odd-row output terminal, said selector operable to drive a same logic level onto both of said output terminals during said testing such that those of said word lines coupled to memory cells in said addressed column carry an inactive logic level.
Claim 2
Dependent Claim
157 words
A memory device, comprising: an address decoder; an array of memory cells arranged in rows and columns, each column having a bit-true and a bit-complement lines coupled to those of said memory cells in said each column, each row having a word line coupled to those of said memory cells in said each row; a read/write circuit coupled to said decoder and to said array, said read/write circuit operable to simultaneously drive first and second test signals respectively onto said bit-true and bit-complement lines of an addressed column during testing of said addressed column; and a memory-row selector coupled to said address decoder and to said array, said selector having an even-row output terminal and an odd-row output terminal, said selector operable to drive a same logic level onto both of said output terminals during said testing such that those of said word lines coupled to memory cells in said addressed column carry an inactive logic level.
Claim 3
Dependent Claim
21 words
The memory device of claim 1 wherein said testing determines a value for the leakage current associated with said chosen column.
Claim 4
Dependent Claim
18 words
The memory device of claim 1 wherein said first test signal is unequal to said second test signal.
Claim 5
Dependent Claim
18 words
The memory device of claim 1 wherein said first test signal is equal to said second test signal.
Claim 6
Dependent Claim
41 words
The memory device of claim 1 wherein said read/write circuit is operable to simultaneously drive complementary logic levels onto said bit-true and bit-complement lines of a column during a data write to an addressed memory cell that is in said column.
Claim 7
Dependent Claim
46 words
The memory device of claim 1 wherein said memory-row selector is operable to respectively drive complementary levels onto said output terminals during a data write to an addressed memory cell such that the word line coupled to said addressed memory cell carries an active logic level.
Claim 8
Independent Claim
74 words
A method, comprising: addressing a column of memory cells in a memory array that is arranged in rows and columns, said columns each having a bit-true and a bit-complement lines; uncoupling said memory cells from said bit-true and bit-complement lines of said addressed column with a row-selector circuit; and driving first and second test signals onto said bit-true and bit-complement lines, respectively, while said memory cells are uncoupled from said bit-true and bit-complement lines.
Claim 9
Independent Claim
74 words
A method, comprising: addressing a column of memory cells in a memory array that is arranged in rows and columns, said columns each having a bit-true and a bit-complement lines; uncoupling said memory cells from said bit-true and bit-complement lines of said addressed column with a row-selector circuit; and driving first and second test signals onto said bit-true and bit-complement lines, respectively, while said memory cells are uncoupled from said bit-true and bit-complement lines.
Claim 10
Dependent Claim
40 words
The method of claim 7 wherein: said rows each have a word line; and said uncoupling comprises said row-selector circuit driving an inactive logic level onto all word lines that are coupled to said memory cells of said addressed column.
Claim 11
Dependent Claim
15 words
The method of claim 7 wherein said first test signal equals said second test signal.
Claim 12
Dependent Claim
17 words
The method of claim 7 wherein said first test signal is unequal to said second test signal.
Claim 13
Dependent Claim
26 words
The method of claim 7, further comprising measuring the respective voltages on and the respective currents through said bit-true and bit-complement lines of said addressed column.
Claim 14
Dependent Claim
39 words
The method of claim 7, further comprising measuring the respective voltages on and the respective currents through said bit-true and bit-complement lines of said addressed column to calculate the value of a leakage current associated with said addressed column.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-12-07 | 2002-06-08 | 2002-12-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-12-07 | 2006-06-08 | 2006-12-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-12-07 | 2010-06-08 | 2010-12-08 | $7700.00 | Window Closed / Lapsed |