Static memory long write test

Claim 3

The method of claim 1, wherein the static memory is a static random access memory (SRAM).

Claim 4

The method of claim 1, wherein the static memory is a First In First Out (FIFO) memory.

Claim 5

The method of claim 1, wherein the bitline true is connected to a bitline true load and the bitline complement is connected to a bitline complement load, and the bitline true load and the bitline complement load are turned off when the bitline true and the bitline complement are pulled down to a low logic level during the long write test.

Claim 6

The method of claim 4, wherein the bitline true load and the bitline complement load are turned off for the duration of the long write test by forcing a bus connected to the bitline true load, the bitline complement load, a first pull-down transistor gate, and a second pull-down transistor gate to a predetermined logic level, and wherein the first pull-down transistor gate is connected to the bitline true load and the second pull-down transistor gate is connected to the bitline complement load.

Claim 7

The method of claim 5, wherein the bitline true load is a first transistor gate and the bitline complement load is a second transistor gate.

Claim 8

The method of claim 6, wherein the bitline true load is a first p-channel transistor gate, the bitline complement load is a second p-channel transistor gate, the first pull-down transistor gate is a first n-channel pull-down transistor, and the second pull-down transistor gate is a second n-channel pull-down transistor, such that when the bus is forced to the predetermined logic level, the first p-channel transistor gate and the second p-channel transistor gate are turned off, the first n-channel pull-down transistor and the second n-channel pull-down transistor are turned on, and the bitline true and bitline complement are pulled to a logic low level.

Claim 9

The method of claim 5, wherein the predetermined logic level is a high logic level.

Claim 10

The method of claim 1, wherein each of the memory cells is a Poly-R Load memory cell.

Claim 11

The method of claim 1, wherein each of the memory cells is a 6 Transistor memory cell.

Claim 12

The method of claim 1, wherein the low logic level is equal to ground potential.

Claim 13

The method of claim 1, wherein the bitline true is connected to a first passgate, the bitline complement is connected to a second passgate, a column decode signal is connected to both the first passgate and the second passgate, a first write driver having a first data input signal is connected to the first passgate, and a second write driver having a second data input signal is connected to the second passgate, and wherein the bitline true and the bitline complement are pulled to a low logic level by setting the column decode signal to a predetermined logic level, thus turning on a column of the static memory such that the first write driver and the second write driver force the bitline true and the bitline complement to the low logic level.

Claim 14

The method of claim 12, wherein the first passgate is a first n-channel transistor and the second passgate is a second n-channel transistor, the column decode signal is connected to the gate of the first n-channel transistor and the gate of the second n-channel transistor, and a source/drain of the first passgate is connected to the first write driver and a source/drain of the second passgate is connected to the second write driver.

Claim 15

The method of claim 12, wherein a plurality of columns, having column addresses, of the static memory are turned on by setting the column decode signal to the predetermined logic level, thus overriding the column addresses.

Claim 16

The method of claim 12, further comprising a bitline true load connected to the bitline true, a bitline complement load connected to the bitline complement, and a bus connected to the bitline true load and the bitline complement load, wherein the bitline true load and the bitline complement load are turned off for the duration of the long write test by forcing the bus to the predetermined logic level.

Claim 17

The method of claim 15, wherein the bitline true load and the bitline complement load are a first p-channel transistor gate and a second p-channel transistor gate, respectively.

Claim 18

The method of claim 12, wherein the predetermined logic level is equal to a logic high level.

Claim 19

A memory structure which provides improved long write testing of a static memory, comprising: at least one wordline of a memory cell; a bitline true of the memory cell which is connected to a true bitline load element and a first pull-down transistor; a bitline complement of the memory cell which is connected to a complement bitline load element and a second pull-down transistor; a bus connected to the bitline true load element, the first pull-down transistor, the bitline complement load element, and the second pull-down transistor, wherein after data of a test data pattern has been written to the memory cell, the wordline is turned off during a long write test, and the bitline true and bitline complement are pulled down to a low logic level by forcing the bus to a predetermined logic level such that the bitline true load and the bitline complement load are turned off during the long write test.

Claim 20

A memory structure which provides improved long write testing of a static memory, comprising: at least one wordline of a memory cell; a bitline true of the memory cell which is connected to a true bitline load element and a first pull-down transistor; a bitline complement of the memory cell which is connected to a complement bitline load element and a second pull-down transistor; a bus connected to the bitline true load element, the first pull-down transistor, the bitline complement load element, and the second pull-down transistor, wherein after data of a test data pattern has been written to the memory cell, the wordline is turned off during a long write test, and the bitline true and bitline complement are pulled down to a low logic level by forcing the bus to a predetermined logic level such that the bitline true load and the bitline complement load are turned off during the long write test.

Claim 21

The memory structure of claim 18, wherein the bitline load is a first transistor gate and the bitline complement load is a second transistor gate.

Claim 22

The memory structure of claim 19, wherein the bitline true load is a first p-channel transistor gate, the bitline complement load is a second p-channel transistor gate, the first pull-down transistor gate is a first n-channel pull-down transistor, and the second pull-down transistor gate is a second n-channel pull-down transistor, such that when the bus is forced to the predetermined logic level, the first p-channel transistor gate and the second p-channel transistor gate are turned off, the first n-channel pull-down transistor and the second n-channel pull-down transistor are turned on, and the bitline true and bitline complement are pulled to a logic low level.

Claim 23

The memory structure of claim 18, wherein the predetermined logic level is a high logic level.

Claim 24

The memory structure of claim 18, wherein the memory cell is a Poly-R Load memory cell.

Claim 25

The memory structure of claim 18, wherein the memory cell is a 6 Transistor memory cell.

Claim 26

The memory structure of claim 18, wherein the low logic level is equal to ground potential.

Claim 27

The memory structure of claim 18, wherein the static memory is a static random access memory (SRAM).

Claim 28

The memory structure of claim 18, wherein the static memory is a First In First Out (FIFO) memory.

Claim 29

A memory structure which provides improved long write testing of a static memory, comprising: a bitline true connected to a first transistor of a memory cell; a bitline complement connected to a second transistor of the memory cell; a first passgate connected to the bitline true; a second passgate connected to the bitline complement; a column decode signal connected to the first passgate and the second passgate; a first write driver, having a first data input signal, which is connected to the first passgate; a second write driver, having a second data input signal, which is connected to the second passgate; and a wordline connected to the first transistor and the second transistor of the memory cell, wherein after data of a test data pattern has been written to the memory cell, the wordline is turned off during a long write test, and the bitline true and the bitline complement are pulled to a logic low level by setting the column decode signal to a predetermined logic level, thus turning on a column of the static memory such that the first write driver and the second write driver force the bitline true and the bitline complement to the logic low level.

Claim 30

A memory structure which provides improved long write testing of a static memory, comprising: a bitline true connected to a first transistor of a memory cell; a bitline complement connected to a second transistor of the memory cell; a first passgate connected to the bitline true; a second passgate connected to the bitline complement; a column decode signal connected to the first passgate and the second passgate; a first write driver, having a first data input signal, which is connected to the first passgate; a second write driver, having a second data input signal, which is connected to the second passgate; and a wordline connected to the first transistor and the second transistor of the memory cell, wherein after data of a test data pattern has been written to the memory cell, the wordline is turned off during a long write test, and the bitline true and the bitline complement are pulled to a logic low level by setting the column decode signal to a predetermined logic level, thus turning on a column of the static memory such that the first write driver and the second write driver force the bitline true and the bitline complement to the logic low level.

Claim 31

The memory structure of claim 27, wherein the first passgate is a first n-channel transistor and the second passgate is a second n-channel transistor, the column decode signal is connected to a gate of the first n-channel transistor and a gate of the second n-channel transistor, and a source/drain of the first passgate is connected to the first write driver and a source/drain of the second passgate is connected to the second write driver.

Claim 32

The memory structure of claim 27, wherein a plurality of columns, having column addresses, of the static memory are turned on by setting the column decode signal to the predetermined logic level, thus overriding the column addresses.

Claim 33

The memory structure of claim 27, further comprising a bitline true load connected to the bitline true, a bitline complement load connected to the bitline complement, and a bus connected to the bitline true load and the bitline complement load, wherein the bitline true load and the bitline complement load are turned off for the duration of the long write test by forcing the bus to the predetermined logic level.

Claim 34

The memory structure of claim 30, wherein the bitline true load and the bitline complement load are a first p-channel transistor gate and a second p-channel transistor gate, respectively.

Claim 35

The memory structure of claim 27, wherein the predetermined logic level is equal to a logic high level.

Claim 36

The memory structure of claim 27, wherein the static memory is a static random access memory (SRAM).

Claim 37

The memory structure of claim 27, wherein the static memory is a First In First Out (FIFO) memory.