US5553025A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device executing a memory test in a plurality of test modes
Assignee: PS4 Luxco SARL
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Filing: 1994-09-20
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Granted: 1996-09-03
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Expires: 2014-09-20
Abstract
Abstract A semiconductor memory device comprises an address bus having plural bits for designating addresses included in a first address group assigned to a memory cell array and in a second address group assigned to plural test modes, a first address decoder for decoding addresses in the first address group, and a second address decoder for decoding addresses in the second address group. A test commanding section generates a test commanding signal responsive to any one of addresses assigned to plural test modes. The second decoder acting as a test mode selecting section is activated by the test commanding signal to generate a test mode selecting signal from addresses assigned to the test modes. A test performing section tests inside the memory device in one of the test modes based on the test mode selecting signal. Number of data items to be input for executing a test inside the memory device is reduced without increasing an external pins.
Inventors
- 👤 Yoshinori Haraguchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 10:03
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/46
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
155 words
A semiconductor memory device comprising a substrate, a plurality of memory cells arrayed on said substrate and each having an address included in a first address group, an address bus for supplying an address signal composed of a plurality of bits designated to one of addresses included in said first address group or one of addresses included in a second address group assigned to a plurality of test modes, a first address decoder, operatively connected between said address bus and said memory cells, for decoding addresses of said address signal included in said first address group for said memory cells, a second address decoder, operatively connected to said address bus, for decoding addresses of said address signal included in said second address group, and a test performing section, operatively connected to said second address decoder, for executing a memory test in one of said test modes based on the output of said second address decoder.
Claim 2
Dependent Claim
155 words
A semiconductor memory device comprising a substrate, a plurality of memory cells arrayed on said substrate and each having an address included in a first address group, an address bus for supplying an address signal composed of a plurality of bits designated to one of addresses included in said first address group or one of addresses included in a second address group assigned to a plurality of test modes, a first address decoder, operatively connected between said address bus and said memory cells, for decoding addresses of said address signal included in said first address group for said memory cells, a second address decoder, operatively connected to said address bus, for decoding addresses of said address signal included in said second address group, and a test performing section, operatively connected to said second address decoder, for executing a memory test in one of said test modes based on the output of said second address decoder.
Claim 3
Dependent Claim
197 words
A semiconductor memory device comprising: a substrate; a plurality of memory cells arrayed on said substrate and each having an address included in a first address group; an address bus composed of a plurality of bits for receiving an address signal designating one of addresses included in said first address group or one of addresses included in a second address group assigned to a plurality of test modes; a first address decoder, operatively connected between said address bus and said memory cells, for decoding addresses included in said first address group for said memory cells; a second address decoder, operatively connected to said address bus, for decoding addresses included in said second address group; a test performing section, operatively connected to said second address decoder, for executing a memory test in one of said test modes based on the output of said second address decoder; and a test commanding section, operatively connected to said address bus and said second address decoder, for generating a test commanding signal responsive to any one of addresses included in said second address group, said test commanding signal activating said second address decoder for latching addresses included in said second address group.
Claim 4
Dependent Claim
197 words
A semiconductor memory device comprising: a substrate; a plurality of memory cells arrayed on said substrate and each having an address included in a first address group; an address bus composed of a plurality of bits for receiving an address signal designating one of addresses included in said first address group or one of addresses included in a second address group assigned to a plurality of test modes; a first address decoder, operatively connected between said address bus and said memory cells, for decoding addresses included in said first address group for said memory cells; a second address decoder, operatively connected to said address bus, for decoding addresses included in said second address group; a test performing section, operatively connected to said second address decoder, for executing a memory test in one of said test modes based on the output of said second address decoder; and a test commanding section, operatively connected to said address bus and said second address decoder, for generating a test commanding signal responsive to any one of addresses included in said second address group, said test commanding signal activating said second address decoder for latching addresses included in said second address group.
Claim 5
Dependent Claim
20 words
A semiconductor memory device as defined in claim 2 wherein said test commanding section is composed of a combinational circuit.
Claim 6
Dependent Claim
18 words
A semiconductor memory device as defined in claim 2 wherein said test commanding section includes a sequential circuit.
Claim 7
Dependent Claim
19 words
A semiconductor memory device as defined in claim 4 wherein said sequential circuit includes two flip-flops cascaded in sequence.
Claim 8
Dependent Claim
23 words
A semiconductor memory device as defined in claim 1 wherein said memory device is used for storing image data for a display unit.
Claim 9
Dependent Claim
46 words
The semiconductor memory device as defined in claim 1, wherein said second address decoder is responsive to a logical high or low state of the bits in said second address group of said address signal to switch from a normal operating mode to said test modes.
Claim 10
Dependent Claim
31 words
The semiconductor memory device as defined in claim 1, wherein said memory test is performed only on those said memory cells which are addressable by addresses in said first address group.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-09-03 | 2000-03-04 | 2000-09-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-09-03 | 2004-03-04 | 2004-09-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-09-03 | 2008-03-04 | 2008-09-03 | $7700.00 | Window Closed / Lapsed |