Multiple clocked dynamic sense amplifier

Claim 1

A circuit for use with a memory array, comprising: a sense amplifier connected to an input line and a complementary input line, wherein the sense amplifier senses data on the input line and complementary input line only during a clock pulse applied to a sense amplifier clock input; a clocking circuit connected to the sense amplifier clock input, utilized to enable said sense amplifier to read data on the input line and complementary input line by generating clock pulses, wherein said clocking circuit generates, during a single read cycle of the memory array, a first clock pulse followed after a predetermined time period by a second clock pulse, wherein the single read cycle of the memory array is the period between two consecutive equilibrations of the input line and the complementary input line; and a latch connected to the sense amplifier, wherein the latch stores data sensed by the sense amplifier during the first and second clock pulses.

Claim 7

A method for reading data from a memory array, comprising the steps of: applying a first equilibrating signal to a sense amplifier in preparation for a single read cycle of the memory array, wherein the sense amplifier is connected to the input line and the complementary input line; initially equilibrating an input line and a complementary input line; applying a first clocking signal to the sense amplifier to enable the sense amplifier to read the data on the input line and complementary input line; isolating the sense amplifier from the input line and complementary input line when applying the first clocking signal; reading the data on the input and complementary input lines a first time; providing an output to a latch connected to the sense amplifier as a result of reading the data on the input line and complementary input line; reconnecting the sense amplifier to the input and complementary input lines before applying a second clocking signal to the sense amplifier; applying the second clocking signal to the sense amplifier to enable the sense amplifier to read the data on the input line and complementary input line a second time; reading the data on the input line and complementary input line a second time; and subsequently equilibrating the input line and the complementary input line, wherein the input and complementary input lines are not equilibrated between the initial equilibrating step and the subsequent equilibrating step.

Claim 8

A method for reading data from a memory array, comprising the steps of: applying a first equilibrating signal to a sense amplifier in preparation for a single read cycle of the memory array, wherein the sense amplifier is connected to the input line and the complementary input line; initially equilibrating an input line and a complementary input line; applying a first clocking signal to the sense amplifier to enable the sense amplifier to read the data on the input line and complementary input line; isolating the sense amplifier from the input line and complementary input line when applying the first clocking signal; reading the data on the input and complementary input lines a first time; providing an output to a latch connected to the sense amplifier as a result of reading the data on the input line and complementary input line; reconnecting the sense amplifier to the input and complementary input lines before applying a second clocking signal to the sense amplifier; applying the second clocking signal to the sense amplifier to enable the sense amplifier to read the data on the input line and complementary input line a second time; reading the data on the input line and complementary input line a second time; and subsequently equilibrating the input line and the complementary input line, wherein the input and complementary input lines are not equilibrated between the initial equilibrating step and the subsequent equilibrating step.