Dynamic random access memory with improved page-mode performance and method therefor having isolator between memory cells and sense amplifiers

Claim 2

A dynamic random access memory comprising: a memory cell activated by a word line, and providing a differential voltage to true and complement bit lines in response to a bit stored therein when activated; isolation means for coupling said true and complement bit lines to true and complement sense lines, respectively, and for isolating said true and complement bit lines from said true and complement sense lines a predetermined time after a start of an access cycle; a first sense amplifier coupled to said true and complement sense lines, for latching a differential voltage between said true and complement sense lines, in response to said access cycle; and a second sense amplifier coupled to said true and complement bit lines, for latching a differential voltage between said true and complement sense lines in response to a termination of said access cycle.

Claim 3

The dynamic random access memory of claim 1 wherein said first sense amplifier comprises: a first transistor having a first current electrode for receiving a first sense enable signal, a control electrode coupled to said complement sense line, and a second current electrode coupled to said true sense line; a second transistor having a first current electrode coupled to said true sense line, a control electrode coupled to said complement sense line, and a second current electrode for receiving a second sense enable signal; a third transistor having a first current electrode for receiving said first sense enable signal, a control electrode coupled to said true sense line, and a second current electrode coupled to said complement sense line; and a fourth transistor having a first current electrode coupled to said complement sense line, a control electrode coupled to said true sense line, and a second current electrode for receiving said second select signal.

Claim 4

The dynamic random access memory of claim 1 wherein said second sense amplifier comprises: a fifth transistor having a first current electrode for receiving a third sense enable signal, a control electrode coupled to said complementary bit line, and a second current electrode coupled to said true bit line; and a sixth transistor having a first current electrode for receiving said third sense enable signal, a control electrode coupled to said true bit line, and a second current electrode coupled to said complementary bit line.

Claim 5

The dynamic random access memory of claim 1 further comprising column decoding means, for coupling said true and complement sense lines to true and complement input/output lines in response to a column address.

Claim 6

In a dynamic random access memory, the dynamic random access memory including a plurality of memory cells activated by a word line, and providing a differential voltage to corresponding true and complement bit lines of a plurality of bit line pairs in response to a bit stored therein, a method of improving a performance of the dynamic random access memory during a series of page-mode cycles, comprising the steps of: activating the word line at a start of the series of page-mode cycles; providing a bit stored in each memory cell to corresponding true and complement bit lines; latching a differential voltage of each true and complement bit line in a first sense amplifier coupled to corresponding true and complement sense lines, respectively; isolating each true and complement bit line from said corresponding true and complement sense lines; equalizing a voltage between each true and complement bit line; selecting bit line pairs in response to successive column addresses; coupling true and complement sense lines corresponding to said selected bit line pairs to true and complement input/output signal lines, respectively; recoupling each true and complement sense line to corresponding true and complement bit lines, respectively, at an end of the series of page-mode cycles; and providing voltages to said true and complement bit lines indicative of a logic state stored in said first sense amplifier at said end of the series of page-mode cycles.

Claim 7

In a dynamic random access memory, the dynamic random access memory including a plurality of memory cells activated by a word line, and providing a differential voltage to corresponding true and complement bit lines of a plurality of bit line pairs in response to a bit stored therein, a method of improving a performance of the dynamic random access memory during a series of page-mode cycles, comprising the steps of: activating the word line at a start of the series of page-mode cycles; providing a bit stored in each memory cell to corresponding true and complement bit lines; latching a differential voltage of each true and complement bit line in a first sense amplifier coupled to corresponding true and complement sense lines, respectively; isolating each true and complement bit line from said corresponding true and complement sense lines; equalizing a voltage between each true and complement bit line; selecting bit line pairs in response to successive column addresses; coupling true and complement sense lines corresponding to said selected bit line pairs to true and complement input/output signal lines, respectively; recoupling each true and complement sense line to corresponding true and complement bit lines, respectively, at an end of the series of page-mode cycles; and providing voltages to said true and complement bit lines indicative of a logic state stored in said first sense amplifier at said end of the series of page-mode cycles.

Claim 8

The method of claim 5 wherein said step of providing voltages to said true and complement bit lines further comprises the step of latching a differential voltage of each true and complement sense line in a second sense amplifier coupled to said corresponding true and complement bit lines.

Claim 9

A dynamic random access memory comprising: a plurality of word lines; a plurality of differential bit lines pairs intersecting said plurality of word lines; a plurality of memory cells located at intersections of said word lines and said bit line pairs, each memory cell providing a bit stored therein as a differential voltage between true and complement bit lines of a corresponding differential bit line pair when a word line to which said memory cell is coupled is activated; row decoding means for activating a word line in response to a row address; first sense means for sensing a differential voltage between each of said true and complement bit lines of said differential bit line pairs and for latching said sensed differential voltage onto corresponding true and complement sense lines during an access cycle; isolation means coupled to said plurality of differential bit line pairs and to said first sense means, for isolating said differential bit line pairs from said first sense means a predetermined time after a start of said access cycle; and second sense means coupled to each of said true and complement bit line pairs, for sensing a differential voltage between each true and complement sense line pair and for latching said differential voltage onto a corresponding true and complement bit line pair in response to a termination of said access cycle.

Claim 10

A dynamic random access memory comprising: a plurality of word lines; a plurality of differential bit lines pairs intersecting said plurality of word lines; a plurality of memory cells located at intersections of said word lines and said bit line pairs, each memory cell providing a bit stored therein as a differential voltage between true and complement bit lines of a corresponding differential bit line pair when a word line to which said memory cell is coupled is activated; row decoding means for activating a word line in response to a row address; first sense means for sensing a differential voltage between each of said true and complement bit lines of said differential bit line pairs and for latching said sensed differential voltage onto corresponding true and complement sense lines during an access cycle; isolation means coupled to said plurality of differential bit line pairs and to said first sense means, for isolating said differential bit line pairs from said first sense means a predetermined time after a start of said access cycle; and second sense means coupled to each of said true and complement bit line pairs, for sensing a differential voltage between each true and complement sense line pair and for latching said differential voltage onto a corresponding true and complement bit line pair in response to a termination of said access cycle.

Claim 11

The dynamic random access memory of claim 7 further comprising equalization means, coupled to said plurality of differential bit line pairs, for coupling together true and complement bit lines of each differential bit line pair after said isolation means isolates each bit line pair from said sense means.

Claim 12

The dynamic random access memory of claim 8 further comprising: column means for coupling true and complement sense lines selected by a column address to an input/output signal pair in response to a column address; and input/output means coupled to said input/output signal pair, for receiving a data bit and providing said data bit to said input/output signal pair in response to a write cycle, and for providing said data bit in response to a differential voltage between true and complement signal lines of said input/output signal pair in response to a read cycle.

Claim 13

The dynamic random access memory of claim 7 wherein said isolation means couples each bit line to a corresponding sense line in response to an isolation signal.

Claim 14

The dynamic random access memory of claim 10 wherein said first sense means comprises a plurality of sense amplifiers each coupled to corresponding true and complement sense lines and to said column decoding means, each sense amplifier comprising: a first transistor having a first current electrode for receiving a first sense enable signal, a control electrode coupled to the complement sense line, and a second current electrode coupled to the true sense line; a second transistor having a first current electrode coupled to the true sense line, a control electrode coupled to the complement sense line, and a second current electrode for receiving a second sense enable signal; a third transistor having a first current electrode for receiving said first sense enable signal, a control electrode coupled to the true sense line, and a second current electrode coupled to the complement sense line; and a fourth transistor having a first current electrode coupled to the complement sense line, a control electrode coupled to the true sense line, and a second current electrode for receiving said second select signal.

Claim 15

The dynamic random access memory of claim 10 wherein said isolation means comprises: a first transistor having a first current electrode coupled to said true bit line, a control electrode for receiving said isolation signal, and a second current electrode coupled to said true sense line; and a second transistor having a first current electrode coupled to said complement bit line, a control electrode for receiving said isolation signal, and a second current electrode coupled to said complement sense line.