US5031145A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Sense amplifier
Assignee: Hughes Microelectronics Ltd
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Filing: 1990-03-29
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Granted: 1991-07-09
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Expires: 2010-03-29
Abstract
Abstract A sense amplifier for determining the logic state of a memory cell consists of a switch transistor (N2) for receiving current during sensing from the memory cell (NV1), a nonvolatile transistor (NV2) providing a reference current which is compared to a representation of the sensed current through the switch transistor (itself dependent on the state of NV1), a bistable latch (N4P4, N5P5) which is switched into one or other of its states depending on the result of the comparison, and a feedback from the output of the latch (NODE 3) to the gate of the switch transistor (N2) to isolate the amplifier from the memory cell after sensing.
Inventors
- 👤 Andrew M. Lever
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 17:25
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/26; G11C16/28; G11C7/00; G11C7/06; G11C7/062; G11C2207/00; G11C2207/06; G11C2207/063
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
193 words
A sense amplifier for determining the logic state of a memory cell, the memory cell including a floating gate transistor, comprising: switch means for receiving the current passing through said memory cell, said current being at one level representing one logic state of the cell or at a second level, higher than the first level, representing a second logic state of the cell; comparing means for comparing a representation of said current with a reference current to provide first or second comparison outputs dependent on whether the representation current is above or below said representation current respectively, wherein said comparing means includes a floating gate transistor and means for biasing said transistor to provide said reference current; latch means responsive to the output of the comparing means and latching into a first state in response to one of said comparison output states; and feedback means from the output of the latch means to the switch means for switching off the latter to isolate the amplifier in its latched first output state from the memory cell when the current received by the switch means from the memory cell is at said second higher level.
Claim 2
Dependent Claim
193 words
A sense amplifier for determining the logic state of a memory cell, the memory cell including a floating gate transistor, comprising: switch means for receiving the current passing through said memory cell, said current being at one level representing one logic state of the cell or at a second level, higher than the first level, representing a second logic state of the cell; comparing means for comparing a representation of said current with a reference current to provide first or second comparison outputs dependent on whether the representation current is above or below said representation current respectively, wherein said comparing means includes a floating gate transistor and means for biasing said transistor to provide said reference current; latch means responsive to the output of the comparing means and latching into a first state in response to one of said comparison output states; and feedback means from the output of the latch means to the switch means for switching off the latter to isolate the amplifier in its latched first output state from the memory cell when the current received by the switch means from the memory cell is at said second higher level.
Claim 3
Dependent Claim
35 words
An amplifier according to claim 1 further comprising means for providing a representation current which is higher than said reference current when the current received by said switch means is at said second, higher level.
Claim 4
Dependent Claim
25 words
An amplifier according to claim 2 wherein the switch means is coupled to a current mirror which supplies said representation current to said comparing means.
Claim 5
Dependent Claim
27 words
An amplifier according to claim 1 wherein said switch means comprises an MOS transistor and said feedback means is coupled to a control gate of said transistor.
Claim 6
Dependent Claim
41 words
An amplifier according to claim 1 wherein the output of said latch means is connected to the control gates of a pair of series CMOS transistors and wherein the output of said amplifier is provided at the junction of said transistors.
Claim 7
Dependent Claim
41 words
An amplifier according to any of claims 1 to 5 in combination with a plurality of memory cells connected to said switch means, select means being provided to enable any one of said memory cells to pass current to said amplifier.
Claim 8
Dependent Claim
20 words
A combination according to claim 6 wherein each memory cell comprises a floating gate non-volatile transistor as its memory element.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-07-08 | 1995-01-07 | 1995-07-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-07-08 | 1999-01-07 | 1999-07-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-07-08 | 2003-01-07 | 2003-07-09 | $7700.00 | Window Closed / Lapsed |