Resistor sensing bit switch

Claim 2

A data storage circuit comprising A. a memory storage cell having a first access means at which data is to be read and stored in said cell; B. readout means for a. indicating the state of said memory cell during read operation, and b. having a second access means; C. a transistor; third and fourth access means having the emitter-collector path of said transistor connected therebetween. D. first coupling means for electrically connecting said first and third access means; E. second coupling means for electrically connecting said second and fourth access means; F. control means coupled to the base of said transistor for forward biasing of said transistor during reading and writing of data in said cell, and reverse biasing of said transistor when said cell is not accessed; G. data input means coupled to said fourth access means for controlling storage of data in said cell during write operation.

Claim 3

The circuit of claim 1 wherein said control means comprises: A. a second transistor having a collector-emitter path connected in series with a resistivE network between first and second control terminals; B. means coupling the base of the first said transistor to an intermediate point on said resistive network to bias the first said transistor on and off when said second transistor is forward and reverse biased, respectively; and C. first and second signal sources to apply corresponding first and second control signals to a respective one of said first and second control terminals whereat said first and second control signals are applied concurrently at levels sufficient to forward-bias said second transistor with reverse-bias thereof in the absence of concurrent application of both said first and second control signals.

Claim 4

The circuit of claim 1 including load means coupled to said fourth access means and responsive to said data input means and said transistor for generating voltage levels corresponding to the status and entry of data in said storage cell.

Claim 5

The circuit of claim 3 wherein said control means comprises: A. a second transistor having a collector-emitter path connected in series with a resistive network between first and second control terminals; B. means coupling the base of the first said transistor to an intermediate point on said resistive network to bias the first said transistor on and off when said second transistor is forward and reverse biased, respectively; and C. first and second signal sources to apply corresponding first and second control signals to a respective one of said first and second control terminals whereat said first and second control signals are applied concurrently at levels sufficient to forward-bias said second transistor with reverse-bias thereof in the absence of concurrent application of both said first and second control signals.

Claim 6

The circuit of claim 3 wherein said second coupling means comprises a normally forward-biased second transistor having an emitter-collector path connected between said second and fourth access means, and second control means coupled to the base of said second transistor for reverse-biasing thereof to isolate said readout means from said fourth access means during write operation when a desired data state is to be stored in said memory cell.

Claim 7

The circuit of claim 5 wherein the first said control means comprises: A. a third transistor having a collector-emitter path connected in series with a resistive network between first and second control terminals; B. means coupling the base of the first said transistor to an intermediate point on said resistive network to bias the first said transistor on and off when said third transistor is forward and reverse biased, respectively; and C. first and second signal sources to apply corresponding first and second control signals to a respective one of said first and second control terminals whereat said first and second control signals are applied concurrently at levels sufficient to forward-bias said third transistor with reverse-bias thereof in the absence of concurrent application of both said first and second control signals.

Claim 8

The circuit of claim 5 wherein said data input means comprises a normally reverse-biased third transistor having an emitter-collector path connected between a reference potential and said fourth access means, and third control means coupled to the base of said third transistor for control of the bias thereof during write operations in accordance with the data status to be stored in said memory cell.

Claim 9

The circuit of claim 7 wherein the first said control means comprises: A. a fourth transistor having a collector-emitter path connected in series with a resistive network between first and second control terminals; B. means coupling the base of the first said transistor to an intermediate point on said resistive network to bias the first said transistor on and off when said fourth said transistor is forward and reverse biased, respectively; and C. first and second signal sources tO apply corresponding first and second control signals to a respective one of said first and second control terminals whereat said first and second control signals are applied concurrently at levels sufficient to forward-bias said fourth transistor with reverse-bias thereof in the absence of concurrent application of both said first and second control signals.

Claim 10

A data storage circuit comprising: A. a flip-flop memory circuit means having first and second output means each of which may assume a different one of two selected potentials to represent a unit of data; B. a pair of first and second transistors with the emitter-collector path of said first transistor coupled between said first output means and a first access means, and with the emitter-collector path of said second transistor connected between said second output means and a second access means; C. control means coupled to the bases of said first and second transistor for simultaneous a. forward biasing each thereof during read and write operations; and b. reverse biasing each thereof when said memory cell is not accessed; D. readout means for a. indicating the state of said memory circuit during read operation; and b. having input means connected to said first and second access means; E. data input means coupled to said first and second access means for controlling storage of data in said memory means during write operations.

Claim 11

A data storage circuit comprising: A. a flip-flop memory circuit means having first and second output means each of which may assume a different one of two selected potentials to represent a unit of data; B. a pair of first and second transistors with the emitter-collector path of said first transistor coupled between said first output means and a first access means, and with the emitter-collector path of said second transistor connected between said second output means and a second access means; C. control means coupled to the bases of said first and second transistor for simultaneous a. forward biasing each thereof during read and write operations; and b. reverse biasing each thereof when said memory cell is not accessed; D. readout means for a. indicating the state of said memory circuit during read operation; and b. having input means connected to said first and second access means; E. data input means coupled to said first and second access means for controlling storage of data in said memory means during write operations.

Claim 12

The circuit of claim 9 wherein said control means comprises: A. a third transistor having a collector-emitter path connected in series with a resistive network between first and second control terminals; B. means coupling the bases of the first and second transistors to an intermediate point on said resistive network to concurrently bias both said first and second transistors on and off when said third transistor is forward and reverse biased, respectively; and C. first and second signal sources to apply corresponding first and second control signals to al respective one of said first and second control terminals whereat said first and second control signals are applied concurrently at levels sufficient to forward-bias said third transistor with reverse-bias thereof in the absence of concurrent application of both said first and second control signals.

Claim 13

The circuit of claim 9 including first and second load means coupled to respective ones of said first and second access means, with said first and second load means responsive to said data input means and corresponding ones of said first and second transistors for generating voltage levels corresponding to the status and entry of data in said memory means.

Claim 14

The circuit of claim 11 wherein said control means comprises: A. a third transistor having a collector-emitter path connected in series with a resistive network between first and second control terminals; B. means coupling the bases of the first and second transistors to an intermediate point on said resistive network to concurrently bias both said first and second transistors on and off when said third transistor is forward and reverse biased, respectively; and C. first and second signal sources to apply corresponding first and second control signals to a respective one of said first and second control terminals whereat said first and second control signals are applied concurrently at levels sufficient to forward-bias said third transistor with reverse-bias thereof in the absence of concurrent application of both said first and second control signals.

Claim 15

The circuit of claim 11 including: A. a third transistor having its emitter-collector path connected in series between said readout input means and said first access means; B. a fourth transistor having its emitter-collector path connected in series between said readout input means and said second access means, and C. second control means coupled to the bases of said third and fourth transistors foR concurrent reverse-biasing each thereof to isolate said readout means during write operations.

Claim 16

The circuit of claim 13 wherein the first said control means comprises: A. a fifth transistor having a collector-emitter path connected in series with a resistive network between first and second control terminals; B. means coupling the base of said first and second transistors to an intermediate point on said resistive network to concurrently bias both said first and second transistors on and off when said fifth transistor is forward and reverse biased, respectively; and C. first and second signal sources to apply corresponding first and second control signals to a respective one of said first and second control terminals whereat said first and second control signals are applied concurrently at levels sufficient to forward-bias said fifth transistor with the reverse-bias thereof in the absence of concurrent application of both said first and second control signals.

Claim 17

The circuit of claim 13 wherein said data input means comprise fifth and sixth transistors, with the emitter-collector path of said fifth transistor connected between a reference potential and said first access means, and with the emitter-collector path of said sixth transistor connected between said source of potential and said second access means; and third control means coupled to the bases of said fifth and sixth transistors for selective biasing thereof in accordance with the required data status to be stored in said memory means.

Claim 18

The circuit of claim 15 wherein the first said control means comprises: A. a seventh transistor having a collector-emitter path connected in series with a resistive network between first and second control terminals; B. means coupling the bases of said first and second transistors to an intermediate point on said resistive network to concurrently bias both said first and second transistors on and off when said seventh transistor is forward and reverse biased, respectively; and C. first and second signal sources to apply corresponding first and second control signals to a respective one of said first and second control terminals whereat said first and second control signals are applied concurrently at levels sufficient to forward-bias said seventh transistor with reverse-bias thereof in the absence of concurrent application of both said first and second control signals.

Claim 19

The circuit of claim 9 wherein said memory means comprises a memory cell of third and fourth transistors having the collectors and bases thereof cross-coupled to form a bistable circuit with A. the emitter-collector path of said third transistor connected in series with said first output means; and B. the emitter-collector of said fourth transistor connected in series with said second output means; and source means biasing said third and fourth transistors for bistable operation.

Claim 20

The circuit of claim 17 wherein the first said control means comprises A. a fifth transistor having a collector-emitter path connected in series with a resistive network between first and second control terminals; B. means coupling the bases of said first and second transistors to an intermediate point on said resistive network to concurrently bias both said first and second transistors on and off when said fifth transistor is forward and reverse biased, respectively; and C. first and second signal sources to apply corresponding first and second control signals to a respective one of said first and second control terminals whereat said first and second control signals are applied concurrently at levels sufficient to forward-bias said fifth transistor with reverse-bias thereof in the absence of concurrent application of both said first and second control signals.

Claim 21

The circuit of claim 17 including first and second load means coupled to respective ones of said first and second access means, with said first and seconD load means responsive to said data input means and corresponding ones of said first and second transistors for generating voltage levels corresponding to the status and entry of data in said memory cell.

Claim 22

The circuit of claim 19 wherein the first said control means comprises: A. a fifth transistor having a collector-emitter path connected in series with a resistive network between first and second control terminals; B. means coupling the base of said first and second transistors to an intermediate point on said resistive network to concurrently bias both said first and second transistors on and off when said fifth transistor is forward and reverse biased, respectively; and C. first and second signal sources to apply corresponding first and second control signals to a respective one of said first and second control terminals whereat said first and second control signals are applied concurrently at levels sufficient to forward-bias said fifth transistor with reverse-bias thereof in the absence of concurrent application of both said first and second control signals.

Claim 23

The circuit of claim 19 including A. a fifth transistor having its emitter-collector path connected in series between said readout input means and said first access means; B. a sixth transistor having its emitter-collector path connected in series between said readout input means and said second access means; and C. second control means coupled to the bases of said fifth and sixth transistors for concurrent reverse-biasing each thereof to isolate said readout means during write operations.

Claim 24

The circuit of claim 21 wherein the first said control means comprises: A. a seventh transistor having a collector-emitter path connected in series with a resistive network between first and second control terminals; B. means coupling the base of said first and second transistor to an intermediate point on said resistive network to concurrently bias both said first and second transistors on and off when said seventh transistor is forward and reverse biased, respectively; and C. first and second signal sources to apply corresponding first and second control signals to respective ones of said first and second control terminals whereat said first and second control signals are applied concurrently at levels sufficient to forward-bias said seventh transistor with reverse-bias thereof in the absence of concurrent application of both said first and second control signals.

Claim 25

The circuit of claim 21 wherein said data input means comprise seventh and eighth transistors, with the emitter-collector path of said seventh transistor connected between a reference potential and said first access means, and with the emitter-collector path of said eighth transistor connected between said source of potential and said second access means; and third control means coupled to the bases of said seventh and eighth transistors for selective biasing thereof to provide required voltage levels at said load means with the required data status of said memory means.

Claim 26

The circuit of claim 23 wherein the first said control means comprises: A. a ninth transistor having a collector-emitter path connected in series with a resistive network between first and second control terminals; B. means coupling the bases of both said first and second transistor to an intermediate point on said resistive network to concurrently bias both said first and second transistors on and off when said ninth transistor is forward and reverse biased, respectively; and C. first and second signal sources to apply corresponding first and second control signals to respective ones of said first and second control terminals whereat said first and second control signals are concurrently applied at sufficient levels to forward-bias said ninth transistor with reverse-bias thereof in the absence of concurrent application of both said first and second control signals.

Claim 27

The ciRcuit of claim 9 wherein said memory means comprises a memory cell of third and fourth multiemitter trigger transistors having the collectors and bases thereof crossed-coupled to form a bistable circuit with A. first emitters of said trigger transistors connected together, and B. second emitters of said trigger transistors coupled to a corresponding one of said first and second output means, and C. bilevel source means providing a first standby potential level and a second access potential level across said trigger transistors with said first potential level in conjunction with the reverse bias of said first and second transistors a. forward-biasing a said first emitter on a data storage controlled conducting one of said trigger transistors with respect to the corresponding base thereof, and b. reverse-biasing a second emitter of the data storage controlled conducting trigger transistor with respect to the base thereof, with said second potential level a. in conjunction with the reverse-bias of said first and second transistors during power-up of said memory cell i. forward-biasing said second emitter of the data storage controlled conducting trigger transistor with respect to the base thereof and ii. increasing the forward-bias on said first emitter of said conducting trigger transistor with respect to the base thereof to a level providing major conduction of the data storage controlled conducting transistor through its said first emitter relative to the second emitter thereof, b. in conjunction with said first and second transistors during access operations forward-biasing a said second emitter of the data storage controlled conducting trigger transistor relative to the base thereof to a level switching major conduction of said conducting trigger transistor through said second emitter with respect to the first emitter thereof, and c. in conjunction with said first and second transistors and with said data input means during write operations, providing conducting forward-bias on a said second emitter of a selected corresponding one of said trigger transistors relative to the base thereof; and D. second control means for selecting said first potential level during stand-by operations and said second potential level during power-up and access operations.

Claim 28

The circuit of claim 25 wherein said bilevel source means includes: A. a like-resistor pair network coupled between the second emitters of said trigger transistors; and B. a complementary source means coupled to said network between its resistor pair to a. reverse-bias said second emitters with respect to their respective bases of said trigger transistors during said standby operation, b. maintaining during ready state operation i. reverse-bias on a said second emitter of the data storage control non-conducting one of said trigger transistors while ii. providing forward-bias on a said second emitter of a data storage control conducting one of said trigger transistors to a level providing major conduction of the data storage control conduction one of said trigger transistors through its said first emitter relative to the second emitter thereof, and c. in conjunction with said bilevel source means during access operation forward-biasing a second emitter of the data storage control conducting one of said trigger transistors to a level switching major conduction of said data storage control conducting trigger transistors through its said second emitter relative to the first emitter thereof.

Claim 29

The circuit of claim 25 wherein the first said control means comprises: A. a fifth transistor having a collector-emitter path connected in series with a resistive network between first and second control terminals; B. means coupling the bases of said first and second transistors to an intermediate point on said resistive network to concurrently bias both the said first and second transistors on and off when saiD fifth transistor is forward and reverse biased, respectively; and C. first and second signal sources to apply corresponding first and second control signals to a respective one of said first and second control terminals whereat said first and second control signals are applied concurrently at levels sufficient to forward-bias said fifth transistor with reverse bias thereof in the absence of concurrent application of both said first and second control signals.

Claim 30

The circuit of claim 27 wherein said bilevel source means includes: A. a second like-resistor pair network coupled between the second emitters of said trigger transistors; and B. a complementary source means coupled to said network between its resistor pair to a. reverse-bias said second emitters with respect to their respective bases of said trigger transistors during said standby operation, b. maintaining during read state operation i. reverse-bias on a said second emitter of the data storage control non-conducting one of said trigger transistors while ii. providing forward-bias on a said second emitter of a data storage control conducting one of said trigger transistors to a level providing major conduction of the data storage control conducting one of said trigger transistors through its said first emitter relative to the second emitter thereof, and c. in conjunction with said bilevel source means during access operation forward-biasing a second emitter of the data storage control conducting one of said trigger transistors to a level switching major conduction of said data storage control conducting trigger transistors through its said second emitter relative to the first emitter thereof.

Claim 31

The circuit of claim 25 including first and second load means coupled to respective ones of said first and second access means, with said first and second load means responsive to said data input means and corresponding ones of said first and second transistors for generating voltage levels corresponding to the status and entry of data in said memory means.

Claim 32

The circuit of claim 29 wherein said bilevel source means includes: A. a like-resistor pair network coupled between the second emitters of said trigger transistors; and B. a complementary source means coupled to said network between its resistor pair to a. reverse-bias said second emitters with respect to their respective bases of said trigger transistors during said standby operation, b. maintaining during ready state operation i. reverse-bias on a said second emitter of the data storage control non-conducting one of said trigger transistors while ii. providing forward-bias on a said second emitter of a data storage control conducting one of said trigger transistors to a level providing major conduction of the data storage control conducting one of said trigger transistors through its said first emitter relative to the second emitter thereof, and c. in conjunction with said bilevel source means during access operation forward-biasing a second emitter of the data storage control conducting one of said trigger transistors to a level switching major conduction of said data storage control conducting trigger transistors through its said second emitter relative to the first emitter thereof.

Claim 33

The circuit of claim 29 wherein the first said control means comprises: A. a fifth transistor having a collector-emitter path connected in series with a resistive network between first and second control terminals; B. means coupling the bases of said first and second transistors to an intermediate point on said resistive network to concurrently bias both the said first and second transistors on and off when said fifth transistor is forward and reverse biased, respectively; and C. first and second signal sources to apply corresponding first and second control signals to a respective one of said first and second control terminals whereat said first and seconD control signals are applied concurrently at levels sufficient to forward-bias said fifth transistor with reverse bias thereof in the absence of concurrent application of both said first and second control signals.

Claim 34

The circuit of claim 31 wherein said bilevel source means includes: A. a second like-resistor pair network coupled between the second emitters of said trigger transistors; and B. a complementary source means coupled to said network between its resistor pair to a. reverse-bias said second emitters with respect to their respective bases of said trigger transistors during said standby operation, b. maintaining during ready state operation i. reverse-bias on a said second emitter of the data storage control non-conducting one of said trigger transistors while ii. providing forward-bias on a said second emitter of the data storage control conducting one of said trigger transistors to a level providing major conduction of the data storage control conducting one of said trigger transistors through its said first emitter relative to the second emitter thereof, and c. in conjunction with said bilevel source means during access operation forward-biasing a second emitter of the data storage control conducting one of said trigger transistors to a level switching major conduction of said data storage control conducting trigger transistors through its said second emitter relative to the first emitter thereof.

Claim 35

The circuit of claim 29 including: A. a fifth transistor having its emitter-collector path coupled in series between said readout input means and said first access means; B. a sixth transistor having its emitter-collector path coupled in series between said readout input means and said second access means; and C. third control means coupled to the bases of said fifth and sixth transistors for concurrent reverse-biasing each thereof to isolate said readout means during write operations.

Claim 36

The circuit of claim 33 wherein said bilevel source means includes A. a like-resistor pair network coupled between the second emitters of said trigger transistors; and B. a complementary source means coupled to said network between its resistor pair to a. reverse-bias said second emitters with respect to their respective bases of said trigger transistors during said standby operation, b. maintaining during ready state operation i. reverse-bias on a said second emitter of the data storage control non-conducting one of said trigger transistors while ii. providing forward-bias on a said second emitter of a data storage control conducting one of said trigger transistors to a level providing major conduction of the data storage control conducting one of said trigger transistors through its said first emitter relative to the second emitter thereof, and c. in conjunction with said bilevel source means during access operation forward-biasing a second emitter of the data storage control conducting one of said trigger transistors to a level switching major conduction of said data storage control conducting trigger transistors through its said second emitter relative to the first emitter thereof.

Claim 37

The circuit of claim 33 wherein the first said control means comprises: A. a seventh transistor having a collector-emitter path connected in series with a resistive network between first and second control terminals; B. means coupling the bases of said first and second transistors to an intermediate point on said resistive network to concurrently bias both said first and second transistors on and off when said seventh transistor is forward and reverse biased, respectively; and C. first and second signal sources to apply corresponding first and second control signals to a respective one of said first and second control terminals whereat said first and second control signals are applied concurrently at sufficient levels to forward-bias said seventh transistor with reverse-bias thereof in the absence of concurrent application of both said first and second control signals.

Claim 38

The circuit of claim 35 wherein said bilevel source means includes: A. a second like-resistor pair network coupled between the second emitters of said trigger transistors; and B. a complementary source means coupled to said network between its resistor pair to a. reverse-bias said second emitters with respect to their respective bases of said trigger transistors during said standby operation, b. maintaining during ready state operation i. reverse-bias on a said second emitter of the data storage control non-conducting one of said trigger transistors while ii. providing forward-bias on a said second emitter of a data storage control conducting one of said trigger transistors to a level providing major conduction of the data storage control conducting one of said trigger transistors through its said first emitter relative to the second emitter thereof, and c. in conjunction with said bilevel source means during access operation forward-biasing a second emitter of the data storage control conducting one of said trigger transistors to a level switching major conduction of said data storage control conducting trigger transistors through its said second emitter relative to the first emitter thereof.

Claim 39

The circuit of claim 33 wherein said data input means comprise seventh and eighth transistors, with the emitter-collector path of said seventh transistor coupled between a reference potential and said first access means, and with the emitter-collector path of said eighth transistor coupled between said source of potential and said second access means; and fourth control means coupled to the bases of said seventh and eighth transistors for selective biasing thereof in accordance with the required data status of said memory cell.

Claim 40

The circuit of claim 37 wherein said bilevel source means includes: A. a like-resistor pair network coupled between the second emitters of said trigger transistors; and B. a complementary source means coupled to said network between its resistor pair to a. reverse-bias said second emitters with respect to their respective bases of said trigger transistors during said standby operation, b. maintaining during ready state operation i. reverse-bias on a said second emitter of the data storage control non-conducting one of said trigger transistors while ii. providing forward-bias on a said second emitter of a data storage control conducting one of said trigger transistors to a level providing major conduction of the data storage control conducting one of said trigger transistors through its said first emitter relative to the second emitter thereof, and c. in conjunction with said bilevel source means during access operation forward-biasing a second emitter of the data storage control conducting one of said trigger transistors to a level switching major conduction of said data storage control conducting trigger transistors through its said second emitter relative to the first emitter thereof.

Claim 41

The circuit of claim 37 wherein the first said control means comprises: A. a ninth transistor having a collector-emitter path connected in series with a resistive network between first and second control terminals; B. means coupling the bases of said first and second transistors to an intermediate point on said resistive network concurrently to bias both said first and second transistors on and off when said ninth transistor is forward and reverse biased, respectively; and C. first and second signal sources to apply corresponding first and second control signals to a respective one of said first and second control terminals whereat said first and second control signals are applied concurrently at sufficient levels to forward-bias said ninth transistor on with reverse bias thereof in the absence of concurrent application of both saId first and second control signals.

Claim 42

The circuit of claim 39 wherein said bilevel source means includes A. a second like-resistor pair network coupled between the second emitters of said trigger transistors; and B. a complementary source means coupled to said network between its resistor pair to a. reverse-bias said second emitters with respect to their respective bases of said trigger transistors during said standby operation, b. maintaining during ready state operation i. reverse-bias on a said second emitter of the data storage control non-conducting one of said trigger transistors while ii. providing forward-bias on a said second emitter of a data storage control conducting one of said trigger transistors to a level providing major conduction of the data storage control conducting one of said trigger transistors through its said first emitter relative to the second emitter thereof, and c. in conjunction with said bilevel source means during access operation forward-biasing a second emitter of the data storage control conducting one of said trigger transistors to a level switching major conduction of said data storage control conducting trigger transistors through its said second emitter relative to the first emitter thereof.