US3617772A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Sense amplifier/bit driver for a memory cell
Assignee: International Business Machines Corp
•
Filing: 1969-07-09
•
Granted: 1971-11-02
•
Expires: 1989-07-09
Abstract
Abstract This specification discloses a sense amplifier/bit driver circuit for a monolithic memory storage cell using a double ended bit drive and sensing scheme. Each of the bit lines serving this storage cell is fed to the emitter of a separate transistor of the sense/drive circuit. The collectors of both these transistors are connected to opposite ends of a differential sense amplifier while the bases of transistors are connected to a diode logic circuit which controls the potential at the base. By changing the potential at the bases of the transistors, conduction through the transistors may be varied in concert or individually for reading and writing of information in the storage cells and for turning the transistors off while the storage cell is not being addressed.
Inventors
- 👤 Klaus G Tertel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 08:07
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/414; G11C11/416; G11C11/411; G11C11/4116
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
302 words
A circuit for sensing output signals from a memory storage cell when the data in the cell is to be read and for the application of drive signals to the cell when data is to be written into the cell comprising: a. input means for the receipt of signals to be sensed from the storage cell and the transmissions of drive signals to the cell; b. output means for the transmission of the data from the sensed signals; c. a transistor with an emitter connected to the input means and a collector connected to the output means for the detection of data in the signals to be sensed during the reading of information stored in the cell and for the generation of drive pulses during writing of information into the cell; d. load means coupled to the emitter for generation of potentials due to current from signals received by the input means and from the transistor; and e. base biasing means coupled to the base of the transistor for varying the potential at the base to operate the transistor as a detector while signals are to be sensed and as a driver when data is to be written into the storage cell wherein said base biasing means includes: i. diode means with characteristics matching the base to emitter characteristics of the transistor, said diode having an anode connected to the base of the transistor; ii. a source of potential; iii. a first load means coupling the anode of the diode to one terminal of the source of potential; and iv a second load means coupling a cathode of the diode to the other terminal of the source of potential whereby the potential supplied to the base of the transistor is determined by the relative magnitudes of the first and second load means.
Claim 2
Dependent Claim
302 words
A circuit for sensing output signals from a memory storage cell when the data in the cell is to be read and for the application of drive signals to the cell when data is to be written into the cell comprising: a. input means for the receipt of signals to be sensed from the storage cell and the transmissions of drive signals to the cell; b. output means for the transmission of the data from the sensed signals; c. a transistor with an emitter connected to the input means and a collector connected to the output means for the detection of data in the signals to be sensed during the reading of information stored in the cell and for the generation of drive pulses during writing of information into the cell; d. load means coupled to the emitter for generation of potentials due to current from signals received by the input means and from the transistor; and e. base biasing means coupled to the base of the transistor for varying the potential at the base to operate the transistor as a detector while signals are to be sensed and as a driver when data is to be written into the storage cell wherein said base biasing means includes: i. diode means with characteristics matching the base to emitter characteristics of the transistor, said diode having an anode connected to the base of the transistor; ii. a source of potential; iii. a first load means coupling the anode of the diode to one terminal of the source of potential; and iv a second load means coupling a cathode of the diode to the other terminal of the source of potential whereby the potential supplied to the base of the transistor is determined by the relative magnitudes of the first and second load means.
Claim 3
Dependent Claim
14 words
The circuit of claim 1 wherein said diode means has a multiplicity of cathodes.
Claim 4
Dependent Claim
48 words
The circuit of claim 2 including: a. means for backbiasing the first mentioned cathode of said diode; and b. a second of said cathodes which can be selectively forward or back biased to vary the potential at the emitter of the transistor for writing information into said cell.
Claim 5
Dependent Claim
24 words
The circuit of claim 2 including terminal means coupled to a third of said cathodes for the reception of signals to backbias said transistor.
Claim 6
Dependent Claim
13 words
The circuit of claim 1 wherein said output means is a sense amplifier.
Claim 7
Dependent Claim
12 words
The circuit of claim 1 wherein said load means is a resistor.
Claim 8
Dependent Claim
14 words
The circuit of claim 1 wherein said input means is a memory bit line.
Claim 9
Dependent Claim
325 words
A circuit for sensing output signals from each end of a double ended memory storage cell when the data in the cell is to be read and for the applIcation of drive signals to that cell when data is to be written into the cell comprising: a. input means from each end of the storage cell for the receipt of signals to be sensed from the storage cell and the transmission of drive signals to the cell; b. output means for the transmission of the data from the sensed signals; c. two transistors each with an emitter connected to one of the input means and a collector connected to the output means for the detection of data in the sensed signals during the reading of information stored in the cell and for the generation of drive pulses during writing of information into the cell; d. load means coupled to each emitter for generation of potentials due to current from signals received by the input means and from the transistors; and e. base biasing means coupled to the base of each of the transistors for varying the potential at the base to operate the transistors as detectors while signals are to be sensed and as drivers when data is to be written into the storage cell wherein each of said base biasing means includes: i. diode means with characteristics matching the base to emitter characteristics of the transistors, said diode means having an anode connected to the base of a separate one of the transistors; ii. a source of potential; iii. a first load means for coupling the anode of the diode to one terminal of the source of potential; and iv. a second load means coupling a cathode of the diode to the other terminal of the source of potential whereby the potential supplied to the base of each of the transistors is determined by the relative magnitudes of the first and second load means.
Claim 10
Dependent Claim
325 words
A circuit for sensing output signals from each end of a double ended memory storage cell when the data in the cell is to be read and for the applIcation of drive signals to that cell when data is to be written into the cell comprising: a. input means from each end of the storage cell for the receipt of signals to be sensed from the storage cell and the transmission of drive signals to the cell; b. output means for the transmission of the data from the sensed signals; c. two transistors each with an emitter connected to one of the input means and a collector connected to the output means for the detection of data in the sensed signals during the reading of information stored in the cell and for the generation of drive pulses during writing of information into the cell; d. load means coupled to each emitter for generation of potentials due to current from signals received by the input means and from the transistors; and e. base biasing means coupled to the base of each of the transistors for varying the potential at the base to operate the transistors as detectors while signals are to be sensed and as drivers when data is to be written into the storage cell wherein each of said base biasing means includes: i. diode means with characteristics matching the base to emitter characteristics of the transistors, said diode means having an anode connected to the base of a separate one of the transistors; ii. a source of potential; iii. a first load means for coupling the anode of the diode to one terminal of the source of potential; and iv. a second load means coupling a cathode of the diode to the other terminal of the source of potential whereby the potential supplied to the base of each of the transistors is determined by the relative magnitudes of the first and second load means.
Claim 11
Dependent Claim
15 words
The circuit of claim 8 wherein each said diode means has a multiplicity of cathodes.
Claim 12
Dependent Claim
58 words
The circuit of claim 9 including: a. means for backbiasing the first mentioned cathode of each of said diodes; and b. a second of said cathodes of each of said diodes which can be selectively forward or back biased to vary the potential at the emitter of each of the transistors individually for writing information into said cell.
Claim 13
Dependent Claim
14 words
The circuit of claim 8 wherein said output means is a differential sense amplifier.
Claim 14
Dependent Claim
12 words
The circuit of claim 8 wherein said load means is a resistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-11-01 | 1975-05-03 | 1975-11-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-11-01 | 1979-05-03 | 1979-11-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-11-01 | 1983-05-03 | 1983-11-02 | $7700.00 | Window Closed / Lapsed |