Binary data transfer circuit

Claim 1

IN A COMPUTER CIRCUIT WHICH INCLUDES A DATA SOURCE HAVING FIRST AND SECOND OUTPUT TERMINALS, EACH OF WHICH MAY ASSUME A DIFFERENT ONE OF TWO SELECTED POTENTIALS TO REPRESENT A UNIT OF DATA, A DATA RECEIVING ELEMENT COMPRISING FIRST AND SECOND TRANSISTORS EACH CONNECTED IN A GROUNDED EMITTER CONFIGURATION, EACH TRANSISTOR HAVING A BASE, A COLLECTOR AND AN EMITTER, A FIRST COLLECTOR IMPEDANCE COUPLED TO SAID COLLECTOR OF SAID FIRST TRANSISTOR, A SECOND COLLECTOR IMPEDANCE COUPLED TO SAID COLLECTOR OF SAID SECOND TRANSISTOR, A FIRST RESISTIVE NETWORK COUPLED BETWEEN THE COLLECTOR OF SAID FIRST TRANSISTOR AND THE BASE OF SAID SECOND TRANSISTOR AND A SECOND RESISTIVE NETWORK COUPLED BETWEEN THE COLLECTOR OF SAID SECOND TRANSISTOR CIRCIUT BASE OF SAID FIRST TRANSISTOR, AND A DATA TRANSFER CIRCUIT COMPRISING THIRD AND FOURTH TRANSISTORS EACH HAVING A BASE, AN EMITTER, A COLLECTOR AND AN EMITTER-COLLECTOR PATH BETWEEN THE EMITTER AND COLLECTOR THEREOF, MEANS CONNECTING THE EMITTER-COLLECTOR PATH OF SAID THIRD TRANSISTOR BETWEEN SAID FIRST OUTPUT TERMINAL OF SAID SOURCE, AND AN INTERMEDIATE POINT ON SAID FIRST RESISTIVE NETWORK, MEANS CONNECTING THE EMITTER-COLLECTOR PATH OF SAID FOURTH TRANSISTOR BETWEEN SAID SECOND OUTPUT TERMINAL OF SAID SOURCE AND AN INTERMEDIATE POINT ON SAID SECOND RESISTIVE NETWORK, AND MEANS COUPLED TO THE BASES OF SAID THIRD AND FOURTH TRANSISTORS FOR SUPPLYING SHORT DURATION TRANSFER PULSES THERETO.