Testing circuitry of internal peripheral blocks in a semiconductor memory device and method of testing the same

Claim 2

A circuit for testing the operation of a signal driver and a signal line in a semiconductor memory, comprising: means for communicating a test mode signal indicating selection of a special test mode; a test transistor, having a control electrode coupled to the signal line at a location distant from the signal driver, and having a conduction path with a first end coupled to said communicating means to receive the special test mode signal; and a bias transistor, having a conduction path coupled between a second end of the conduction path of said test transistor and a bias voltage; wherein said test transistor is conductive responsive to receiving said special test mode signal at the first end of its conduction path in combination with receiving an active signal from the signal driver at its control electrode.

Claim 3

The circuit of claim 1, wherein the special test mode signal indicates selection of the special test mode when at a first logic level; and wherein said test transistor has a larger size than that of said bias transistor so that the voltage at the second end of the conduction path of the test transistor is near the first logic level when both said test transistor and said bias transistor are conductive.

Claim 4

The circuit of claim 1, further comprising: response logic coupled to the second end of said test transistor, and coupled to an external terminal of the memory.

Claim 5

The circuit of claim 1, wherein the signal driver comprises a row decoder in the memory; and wherein the signal line comprises a row line in the memory.

Claim 6

The circuit of claim 1, wherein the signal driver comprises a circuit for generating a control signal in the memory.

Claim 7

A semiconductor memory, comprising: a plurality of memory cells arranged in rows and columns; a row decoder, having a plurality of outputs, each coupled to one of a plurality of row lines, for selecting a row of memory cells responsive to a row address by energizing one of the plurality of row lines; circuitry for communicating a special test mode signal indicating, with a first logic level, selection of a special test mode; a first plurality of test transistors, each having a control electrode coupled to an associated row line at a location distant from said row decoder, and having a conduction path with a first end coupled to said communicating circuitry to receive the special test mode signal; and a first bias transistor, having a conduction path coupled between a second end of the conduction path of said each of said first plurality of test transistors and a bias voltage; wherein each of said first plurality of test transistors is conductive responsive to receiving said special test mode signal at the first end of its conduction path in combination with receiving an active row line signal at its control electrode.

Claim 8

A semiconductor memory, comprising: a plurality of memory cells arranged in rows and columns; a row decoder, having a plurality of outputs, each coupled to one of a plurality of row lines, for selecting a row of memory cells responsive to a row address by energizing one of the plurality of row lines; circuitry for communicating a special test mode signal indicating, with a first logic level, selection of a special test mode; a first plurality of test transistors, each having a control electrode coupled to an associated row line at a location distant from said row decoder, and having a conduction path with a first end coupled to said communicating circuitry to receive the special test mode signal; and a first bias transistor, having a conduction path coupled between a second end of the conduction path of said each of said first plurality of test transistors and a bias voltage; wherein each of said first plurality of test transistors is conductive responsive to receiving said special test mode signal at the first end of its conduction path in combination with receiving an active row line signal at its control electrode.

Claim 9

The memory of claim 6, wherein the first ends of the conduction paths of each of said first plurality of test transistors are connected together to receive said special test mode signal in common.

Claim 10

The memory of claim 7, wherein the second ends of the conduction paths of each of said first plurality of test transistors are connected together and to said first bias transistor.

Claim 11

The memory of claim 6, wherein the second ends of the conduction paths of each of said first plurality of test transistors are connected together and to said first bias transistor.

Claim 12

The memory of claim 6, further comprising: a second plurality of test transistors, each having a control electrode coupled to an associated row line at a location distant from said row decoder, and having a conduction path with a first end coupled to said communicating circuitry to receive the special test mode signal; and a second bias transistor, having a conduction path coupled between a second end of the conduction path of said each of said second plurality of test transistors and the bias voltage; wherein each of said second plurality of test transistors is conductive responsive to receiving said special test mode signal at the first end of its conduction path in combination with receiving an active row line signal at its control electrode; and wherein said first and second pluralities of test transistors are associated with alternating ones of said row lines.

Claim 13

The memory of claim 6, wherein said row lines are energized with a voltage corresponding to the first logic level; and wherein the bias voltage corresponds to the first logic level.

Claim 14

A semiconductor memory comprising: a plurality of memory cells arranged in rows and columns; a row decoder for selecting a row of memory cells responsive to a row address by energizing one of a plurality of row lines extending away from said row decoder; a first plurality of test transistors, each having a control electrode coupled to an associated row line at a location distant from said row decoder, and having a conduction path with a first end for receiving a special test mode signal which indicates selection of a special test mode and selection of said first plurality of test transistors when at a first logic level; a first bias transistor, having a conduction path coupled between a second end of the conduction path of said each of said first plurality of test transistor and a bias voltage; and a second plurality of test transistors, each having a control electrode coupled to an associated row line at a location distant from said row decoder, and having a conduction path with a first end for receiving the special test mode signal which indicates selection of the special test mode and selection of said second plurality of test transistors when at the first logic level, and with a second end coupled to said first bias transistor; wherein each of said first and second pluralities of test transistors is conductive responsive to receiving said special test mode signal at the first end of its conduction path in combination with receiving an active row line signal at its control electrode; and wherein said first and second pluralities of test transistors are associated with alternating ones of said row lines.

Claim 15

A semiconductor memory comprising: a plurality of memory cells arranged in rows and columns; a row decoder for selecting a row of memory cells responsive to a row address by energizing one of a plurality of row lines extending away from said row decoder; a first plurality of test transistors, each having a control electrode coupled to an associated row line at a location distant from said row decoder, and having a conduction path with a first end for receiving a special test mode signal which indicates selection of a special test mode and selection of said first plurality of test transistors when at a first logic level; a first bias transistor, having a conduction path coupled between a second end of the conduction path of said each of said first plurality of test transistor and a bias voltage; and a second plurality of test transistors, each having a control electrode coupled to an associated row line at a location distant from said row decoder, and having a conduction path with a first end for receiving the special test mode signal which indicates selection of the special test mode and selection of said second plurality of test transistors when at the first logic level, and with a second end coupled to said first bias transistor; wherein each of said first and second pluralities of test transistors is conductive responsive to receiving said special test mode signal at the first end of its conduction path in combination with receiving an active row line signal at its control electrode; and wherein said first and second pluralities of test transistors are associated with alternating ones of said row lines.

Claim 16

A semiconductor memory, comprising: a plurality of memory cells arranged in rows and columns; a row decoder for selecting a row of memory cells responsive to a row address by energizing one of a plurality of row lines extending away from said row decoder; a first plurality of test transistors, each having a control electrode coupled to an associated row line at a location distant from said row decoder, and having a conduction path with a first end for receiving a special test mode signal which indicates selection of a special test mode when at a first logic level; a first bias transistor, having a conduction path coupled between a second end of the conduction path of said each of said first plurality of test transistor and a bias voltage; a first adjacent test transistor having a conduction path, and having a control electrode coupled to a first row line; and a second adjacent test transistor having a conduction path, and having a control electrode coupled to a second row line adjacent to said first row line; a second bias transistor, having a conduction path coupled on one end to the bias voltage; wherein each of said first plurality of test transistors is conductive responsive to receiving said special test mode signal at the first end of its conduction path in combination with receiving an active row line signal at its control electrode; and wherein the conduction paths of said first and second adjacent test transistors are connected in series between said second bias transistor, on one end, and connected on another end to receive the special test mode signal which indicates selection of the special test mode when at the first logic level.

Claim 17

A semiconductor memory, comprising: a plurality of memory cells arranged in rows and columns; a row decoder for selecting a row of memory cells responsive to a row address by energizing one of a plurality of row lines extending away from said row decoder; a first plurality of test transistors, each having a control electrode coupled to an associated row line at a location distant from said row decoder, and having a conduction path with a first end for receiving a special test mode signal which indicates selection of a special test mode when at a first logic level; a first bias transistor, having a conduction path coupled between a second end of the conduction path of said each of said first plurality of test transistor and a bias voltage; a first adjacent test transistor having a conduction path, and having a control electrode coupled to a first row line; and a second adjacent test transistor having a conduction path, and having a control electrode coupled to a second row line adjacent to said first row line; a second bias transistor, having a conduction path coupled on one end to the bias voltage; wherein each of said first plurality of test transistors is conductive responsive to receiving said special test mode signal at the first end of its conduction path in combination with receiving an active row line signal at its control electrode; and wherein the conduction paths of said first and second adjacent test transistors are connected in series between said second bias transistor, on one end, and connected on another end to receive the special test mode signal which indicates selection of the special test mode when at the first logic level.

Claim 18

A semiconductor memory, comprising: a plurality of memory cells arranged in rows and columns, each of said columns associated with a true and a complement bit line; a write circuit, coupled to true and complement bit lines of a selected column of memory cells, for presenting data to the true and complement bit lines of the selected column of memory cells in a write operation; a plurality of true test transistors, each having a control electrode coupled to an associated true bit line of an associated column, and having a conduction path, said test transistor of a conductivity type so as to be conductive responsive to its associated true bit line being driven to a first voltage level by said write circuit; and a plurality of complement test transistors, each having a control electrode coupled to an associated complement bit line of an associated column, and having a conduction path, said test transistor also of a conductivity type so as to be conductive responsive to its associated complement bit line being driven to the first voltage level by said write circuit; a first bias transistor, having a conduction path coupled between a bias voltage and a first end of the conduction path of each of said true and complement test transistors, and having a control electrode for receiving a signal indicating a special test mode or a normal operating mode, said bias transistor of the conductivity type so as to be conductive responsive to receiving the signal indicating the special test mode and non-conductive responsive to receiving the signal indicating normal operating mode.

Claim 19

A semiconductor memory, comprising: a plurality of memory cells arranged in rows and columns, each of said columns associated with a true and a complement bit line; a write circuit, coupled to true and complement bit lines of a selected column of memory cells, for presenting data to the true and complement bit lines of the selected column of memory cells in a write operation; a plurality of true test transistors, each having a control electrode coupled to an associated true bit line of an associated column, and having a conduction path, said test transistor of a conductivity type so as to be conductive responsive to its associated true bit line being driven to a first voltage level by said write circuit; and a plurality of complement test transistors, each having a control electrode coupled to an associated complement bit line of an associated column, and having a conduction path, said test transistor also of a conductivity type so as to be conductive responsive to its associated complement bit line being driven to the first voltage level by said write circuit; a first bias transistor, having a conduction path coupled between a bias voltage and a first end of the conduction path of each of said true and complement test transistors, and having a control electrode for receiving a signal indicating a special test mode or a normal operating mode, said bias transistor of the conductivity type so as to be conductive responsive to receiving the signal indicating the special test mode and non-conductive responsive to receiving the signal indicating normal operating mode.

Claim 20

The memory of claim 14, wherein said true and complement test transistors each have a larger size than that of said bias transistor so that the voltage at a second end of the conduction path of one of said true and complement test transistors is near the bias voltage when said one of said true and complement test transistors and said bias transistor are both conductive.

Claim 23

The method of claim 16, wherein the active signal is at a logic level corresponding to the first bias voltage.

Claim 24

The method of claim 16, wherein the signal driver comprises a row decoder and the signal line comprises a row line; and wherein said activating step comprises: presenting a row address to the row decoder.

Claim 25

The method of claim 16, wherein the activating step comprises: writing data to a bit line; and wherein the signal line comprises the bit line, and the signal driver comprises a write circuit.