Read/write memory with improved test mode data compare

Claim 2

In a memory having a parallel test mode in which a plurality of on-chip data lines are compared with one another, a data comparator circuit comprising: a first logic function, having a first output node, comprising: a first pull-up device coupled between the first output node and a first bias voltage corresponding to a first logic state, for biasing the first output node to the first bias voltage; and a plurality of pull-down transistors, each having a conduction path coupled between the first output node and a second bias voltage corresponding to a second logic state, and each having a control terminal coupled to an associated one of said plurality of data lines; a second logic function, having a second output node, comprising: a pull-down device coupled between the second output node and the second bias voltage, for biasing the second output node to the second bias voltage; and a plurality of pull-up transistors, each having a conduction path coupled between the second output node and the first bias voltage, and each having a control terminal coupled to an associated one of said plurality of data lines in such a manner that each of said plurality of data lines turns on either its associated pull-up transistor or its associated pull-down transistor with a digital data state communicated thereon; and an output logic function, coupled to said first and second output nodes, for generating a pass signal responsive to said first and second output nodes being at the same logic state, and for generating a fail signal responsive to said first and second output nodes being at different logic states.

Claim 3

The circuit of claim 1, wherein said first pull-up device comprises a first transistor having its conduction path coupled between said first output node and the first bias voltage, and having a control terminal coupled to an enable line; wherein said pull-down device comprises a second transistor having its conduction path coupled between said second output node and the second bias voltage, and having a control terminal coupled to the enable line; and wherein said pull-up device and said pull-down device are each made conductive responsive to the enable line indicating that said circuit is to be enabled, and said pull-up device and said pull-down device are each made non-conductive responsive to the enable line indicating that said circuit is to be disabled.

Claim 4

The circuit of claim 2, wherein said output logic function also receives said enable line at an input, such that said output logic function is enabled to respond to the state of said first and second output nodes responsive to the enable line indicating that said circuit is to be enabled, and is disabled from responding to the state of said first and second output nodes responsive to the enable line indicating that said circuit is to be disabled.

Claim 5

The circuit of claim 3, wherein said first logic function further comprises: a first forcing transistor having its conduction path in parallel with said plurality of pull-down transistors, and having its gate coupled to said enable line in such a manner that the first forcing transistor is off responsive to the enable line indicating that said circuit is to be enabled, and in such a manner that the first forcing transistor is on responsive to the enable line indicating that said circuit is to be disabled; and wherein said second logic function further comprises: a second forcing transistor having its conduction path in parallel with said plurality of pull-up transistors, and having its gate coupled to said enable line in such a manner that the second forcing transistor is off responsive to the enable line indicating that said circuit is to be enabled, and in such a manner that the second forcing transistor is on responsive to the enable line indicating that said circuit is to be disabled.

Claim 6

The circuit of claim 2, wherein each of said plurality of pull-down transistors in said first logic function are sized significantly larger than said pull-up device; and wherein each of said plurality of pull-up transistors in said second logic function are sized significantly larger than said pull-down device.

Claim 7

The circuit of claim 1, wherein said pull-up transistors and said pull-down transistors are field effect transistors having opposite conductivity type relative to one another.

Claim 8

A memory in an integrated circuit, comprising: an array of addressable memory cells; means for selecting a plurality of said memory cells in said array; means for sensing a stored state in said selected plurality of memory cells and communicating the sensed stored state to a plurality of data lines; means, coupled to said plurality of data lines, for communicating the state of one of said data lines to a terminal; and a data comparator, coupled to said plurality of data lines in parallel with said communicating means, for comparing the state of said plurality of data lines with one another, comprising: a first logic function, having a first output node, comprising: a first pull-up device coupled between the first output node and a first bias voltage corresponding to a first logic state, for biasing the first output node to the first bias voltage; and a plurality of pull-down transistors, each having a conduction path coupled between the first output node and a second bias voltage corresponding to a second logic state, and each having a control terminal coupled to an associated one of said plurality of data lines; a second logic function, having a second output node, comprising: a pull-down device coupled between the second output node and the second bias voltage, for biasing the second output node to the second bias voltage; and a plurality of pull-up transistors, each having a conduction path coupled between the second output node and the first bias voltage, and each having a control terminal coupled to an associated one of said plurality of data lines in such a manner that each of said plurality of data lines turns on either its associated pull-up transistor or its associated pull-down transistor with a digital data state communicated thereon; and an output logic function, coupled to said first and second output nodes, for generating a pass signal responsive to said first and second output nodes being at the same logic state, and for generating a fail signal responsive to said first and second output nodes being at different logic states.

Claim 9

A memory in an integrated circuit, comprising: an array of addressable memory cells; means for selecting a plurality of said memory cells in said array; means for sensing a stored state in said selected plurality of memory cells and communicating the sensed stored state to a plurality of data lines; means, coupled to said plurality of data lines, for communicating the state of one of said data lines to a terminal; and a data comparator, coupled to said plurality of data lines in parallel with said communicating means, for comparing the state of said plurality of data lines with one another, comprising: a first logic function, having a first output node, comprising: a first pull-up device coupled between the first output node and a first bias voltage corresponding to a first logic state, for biasing the first output node to the first bias voltage; and a plurality of pull-down transistors, each having a conduction path coupled between the first output node and a second bias voltage corresponding to a second logic state, and each having a control terminal coupled to an associated one of said plurality of data lines; a second logic function, having a second output node, comprising: a pull-down device coupled between the second output node and the second bias voltage, for biasing the second output node to the second bias voltage; and a plurality of pull-up transistors, each having a conduction path coupled between the second output node and the first bias voltage, and each having a control terminal coupled to an associated one of said plurality of data lines in such a manner that each of said plurality of data lines turns on either its associated pull-up transistor or its associated pull-down transistor with a digital data state communicated thereon; and an output logic function, coupled to said first and second output nodes, for generating a pass signal responsive to said first and second output nodes being at the same logic state, and for generating a fail signal responsive to said first and second output nodes being at different logic states.

Claim 10

The memory of claim 7, further comprising: means for enabling said comparator responsive to an external signal indicating that a parallel test mode is to be enabled.

Claim 11

The memory of claim 8, wherein said enabling means drives an enable line at an output thereof, said enable line indicating whether said parallel test mode is enabled or disabled; wherein said pull-up device comprises a first transistor having its conduction path coupled between said first output node and the first bias voltage, and having a control terminal coupled to the enable line; wherein said pull-down device comprises a second transistor having its conduction path coupled between said second output node and the second bias voltage, and having a control terminal coupled to the enable line; and wherein said pull-up device and said pull-down device are each made conductive responsive to the enable line indicating that said circuit is to be enabled, and said pull-up device and said pull-down device are each made non-conductive responsive to the enable line indicating that the parallel test mode is to be disabled.

Claim 12

The memory of claim 9, wherein said output logic function also receives said enable line at an input, such that said output logic function is enabled to respond to the state of said first and second output nodes responsive to the enable line indicating that the parallel test mode is to be enabled, and is disabled from responding to the state of said first and second output nodes responsive to the enable line indicating that the parallel test mode is to be disabled.

Claim 13

The memory of claim 10, wherein said first logic function further comprises: a first forcing transistor having its conduction path in parallel with said plurality of pull-down transistors, and having its gate coupled to said enable line in such a manner that the first forcing transistor is off responsive to the enable line indicating that the parallel test mode is to be enabled, and in such a manner that the first forcing transistor is on responsive to the enable line indicating that the parallel test mode is to be disabled; and wherein said second logic function further comprises: a second forcing transistor having its conduction path in parallel with said plurality of pull-up transistors, and having its gate coupled to said enable line in such a manner that the second forcing transistor is off responsive to the enable line indicating that the parallel test mode is to be enabled, and in such a manner that the second forcing transistor is on responsive to the enable line indicating that the parallel test mode is to be disabled.

Claim 14

The memory of claim 9, wherein each of said plurality of pull-down transistors in said first logic function are sized significantly larger than said pull-up device; and wherein each of said plurality of pull-up transistors in said second logic function are sized significantly larger than said pull-down device.

Claim 15

The memory of claim 7, wherein said pull-up transistors and said pull-down transistors are field effect transistors having opposite conductivity type relative to one another.

Claim 18

The method of claim 14, further comprising: receiving a signal indicating that a parallel test mode is to be enabled; wherein said biasing steps are performed responsive to said receiving step.

Claim 19

The method of claim 15, further comprising: generating an enable signal responsive to said receiving step; wherein said step of biasing said first node comprises: turning on a first biasing transistor, having its conduction path coupled between said first node and the first voltage; and wherein said step of biasing said second node comprises: turning on a second biasing transistor, having its conduction path coupled between said second node and the second voltage.

Claim 20

The method of claim 16, further comprising: receiving a signal indicating that a parallel test mode is to not be enabled and generating a disable signal responsive thereto; and responsive to the generating of a disable signal, turning on a first forcing transistor having its conduction path coupled between said first node and the second voltage, and turning on a second forcing transistor having its conduction path coupled between said second node and the first voltage.