Full memory chip long write test mode

Claim 3

The method of claim 1, wherein in placing the first memory block into the long write test mode, also turning on the plurality of columns within the first memory block and in placing the second memory block into the long write test mode, also turning on the plurality of columns of the second memory block.

Claim 4

The method of claim 1, wherein, in placing the first memory block and the second memory block into the long write test mode, the bitlines true of the first memory block and the bitlines true of the second memory block are forced to the low logic level.

Claim 5

The method of claim 1, wherein, in placing the first memory block and the second memory block into the long write test mode, the bitlines true and the bitlines complement of the first memory block and the bitlines true and the bitlines complement of the second memory block are forced to the low logic level.

Claim 6

The method of claim 1, wherein all of the plurality of memory blocks of the memory chip are placed into the long write test mode.

Claim 7

The method of claim 1, wherein the memory chip is a Static Random Access Memory (SRAM).

Claim 8

The method of claim 1, wherein each memory block of the plurality of memory blocks remains in the long write test mode until selected again.

Claim 9

The method of claim 1, wherein a plurality of bitline load elements are connected to the plurality of bitlines true and bitlines complement of the first memory block and the bitline load elements of the first memory block are turned off when the first memory block is placed in the long write test mode, and wherein a plurality of bitline load elements are connected to the plurality of bitlines true and bitlines complement of the second memory block and the bitline load elements of the second memory block are turned off when the second memory block is placed in the long write test mode.

Claim 10

The method of claim 1, wherein after the step of placing the first memory block and the second memory block of the plurality of memory blocks into the long write test mode, comprising the further steps of: exiting the first memory block of the plurality of memory blocks from the long write test mode by reselecting the first memory block; placing the first memory block of the plurality of memory blocks into a read disturb test mode upon selecting the first memory block, and allowing the wordlines of the first memory block to be enabled and not forcing the bitlines true or the bitlines complement of the first memory block to the low logic level, wherein the first memory block of the plurality of memory blocks remains in the read disturb test mode while selected; exiting the second memory block of the plurality of memory blocks from the long write test mode by reselecting the second memory block; and placing the second memory block of the plurality of memory blocks into the read disturb test mode upon selecting the second memory block, and allowing the wordlines of the second memory block to be enabled and not forcing the bitlines true or the bitlines complement of the second memory block to the low logic level, wherein the second memory block of the plurality of memory blocks remains in the read disturb test mode while selected, wherein placing the first memory block into the read disturb test mode followed by placing the second memory block into the read disturb test mode constitutes a "domino" style entry into the read disturb test mode.

Claim 11

The method of claim 9, wherein after the steps of placing the first memory block and the second memory block of the plurality of memory blocks into the long write test mode and before the step of placing the first memory block of the plurality of memory blocks into the read disturb mode, comprising the additional step of: performing a pause to cause a long write disturb of the memory chip.

Claim 12

The method of claim 9, wherein all of the plurality of memory blocks of the memory chip are placed into the read disturb test mode.

Claim 13

The method of claim 9, wherein the long write test mode is represented by a first state and the read disturb test mode is represented by a second state.

Claim 14

The method of claim 12, wherein the first state and the second state are generated by a state machine circuit, which is associated with each memory block of the memory chip, comprising: a logic element, which has a block select signal as a first input signal and a delay signal as a second input signal and which produces a pulsed clock signal upon selection of the memory block; a delay element, which has the block select signal as an input signal and which produces the delay signal as an output signal; a first clocked Flip Flop which receives a long write signal as a first input signal, the pulsed clocked signal as a second input signal used for clocking the first clocked Flip Flop, and produces a first output signal; and a second clocked Flip Flop which receives the first output signal of the first clocked Flip Flop as a first input signal, the pulsed clocked signal as a second input signal for clocking the second clocked Flip Flop, and produces a second output signal.

Claim 15

The method of claim 13, wherein the first output signal, the second output signal, and the block select signal are utilized by block row enable circuitry to generate an output, signal capable of enabling the rows of a memory block of the plurality of memory blocks.

Claim 16

The method of claim 13, wherein the first output signal, the second output signal, and the block select signal are utilized by block column enable circuitry to generate an output signal capable of enabling the columns of a memory block of the plurality of memory blocks.

Claim 17

The method of claim 13, wherein the first output signal, the second output signal, the block select signal, and an edge transition detection signal are utilized by block edge transition detection circuitry to generate an output signal capable of detecting the edge transition of an input signal to the memory chip and communicating this detection to the memory block.

Claim 18

The method of claim 13, wherein the first output signal, the second output signal, the block select signal, and a write signal are utilized by block write enable circuitry to generate an output signal capable of enabling write control of a memory block of the plurality of memory blocks.

Claim 21

The method of claim 18, wherein in placing the first memory block into the long write test mode, also turning on the plurality of columns of the first memory block and in placing the second memory block into the long write test mode, also turning on the plurality of columns of the second memory block.

Claim 22

The method of claim 18, wherein, in placing the first memory block and the second memory block into the long write test mode, the bitlines true of the first memory block and the bitlines true of the second memory block are forced to the low logic level.

Claim 23

The method of claim 18, wherein, in placing the first memory block and the second memory block into the long write test mode, the bitlines true and the bitlines complement of the first memory block and the bitlines true and the bitlines complement of the second memory block are forced to the low logic level.

Claim 24

The method of claim 18, wherein the memory chip is a Static Random Access Memory (SRAM).

Claim 25

The method of claim 18, wherein the memory chip is a multiple port memory.

Claim 26

The method of claim 18, wherein a plurality of bitline load elements are connected to the plurality of bitlines true and bitlines complement of the first memory block and a plurality of bitline load elements are connected to the plurality of bitlines true and bitlines complement of the second memory block, and the bitline load elements of the first memory block and the second memory block are turned off in the long write test mode.

Claim 27

The method of claim 18, wherein after the step of placing the second memory block into the long write test mode, comprising the further steps of: exiting the first memory block of the plurality of memory blocks from the long write test mode by reselecting the first memory block; placing the first memory block into a read disturb test mode upon selecting the first memory block, and allowing the wordlines of the first memory block to be enabled and not forcing the bitlines true or the bitlines complement of the first memory block to the low logic level, wherein the first memory block remains in the read disturb test mode while selected; exiting the second memory block of the plurality of memory blocks from the long write test mode by reselecting the second memory block; and placing the second memory block into the read disturb test mode upon selecting the second memory block, and allowing the wordlines of the second memory block to be enabled and not forcing the bitlines true or the bitlines complement of the second memory block to the low logic level, wherein the second memory block remains in the read disturb test mode while selected.

Claim 28

The method of claim 25, wherein after the steps of placing the first memory block and the second memory block of the plurality of memory blocks into the long write test mode and before the step of placing the first memory block of the plurality of memory blocks into the read disturb mode, comprising the additional step of: performing a pause to cause a long write disturb of the memory chip.

Claim 29

The method of claim 25, wherein the long write test mode is represented by a first state and the read disturb test mode is represented by a second state.

Claim 30

The method of claim 27, wherein the first state and the second state are generated by a state machine circuit, which is associated with each memory block of the memory chip, comprising: a logic element, which has a block select signal as a first input signal and a delay signal as a second input signal and which produces a pulsed clock signal upon selection of a memory block; a delay element, which has the block select signal as an input signal and which produces the delay signal as an output signal; a first clocked Flip Flop which receives a long write signal as a first input signal, the pulsed clocked signal as a second input signal used for clocking the first clocked Flip Flop, and produces a first output signal; and a second clocked Flip Flop which receives the first output signal of the first clocked Flip Flop as a first input signal, the pulsed clocked signal as a second input signal used for clocking the second clocked Flip Flop, and produces a second output signal.

Claim 31

The method of claim 28, wherein the first output signal, the second output signal, and the block select signal are utilized by block row enable circuitry to generate an output signal capable of enabling the rows of an associated memory block of the plurality of memory blocks.

Claim 32

The method of claim 28, wherein the first output signal, the second output signal, and the block select signal are utilized by block column enable circuitry to generate an output signal capable of enabling the columns of an associated memory block of the plurality of memory blocks.

Claim 33

The method of claim 28, wherein the first output signal, the second output signal, the block select signal, and an edge transition detection signal are utilized by block edge transition detection circuitry to generate an output signal capable of detecting the edge transition of an input signal of the memory chip and communicating this detection to an associated memory block of the plurality of memory blocks.

Claim 34

The method of claim 28, wherein the first output signal, the second output signal, the block select signal, and a write signal are utilized by block write enable circuitry to generate an output signal capable of enabling write control of an associated memory block of the plurality of memory blocks.

Claim 35

A structure for performing long write testing of a memory chip comprising: a memory chip divided into a plurality of memory blocks, with each memory block of the plurality of memory blocks having a plurality of memory cells, a plurality of rows, a plurality of columns, a plurality of wordlines, a plurality of bitlines true, and a plurality of bitlines complement; a plurality of block select signals, with each block select signal associated with a memory block; means, associated with a first memory block of the plurality of memory blocks, for placing the first memory block of the plurality of memory blocks into a long write test mode upon selecting the first memory block, and turning off the plurality of wordlines of the first memory block and forcing at least the bitlines true or the bitlines complement of the first memory block to a low logic level wherein the first memory; block remains in the long write test mode until selected again; and means, associated with a second memory block of the plurality of memory blocks, for placing the second memory block of the plurality of memory blocks into the long write test mode upon selecting the second memory block, and turning off the plurality of wordlines of the second memory block and forcing at least the bitlines true or the bitlines complement of the second memory block to the low logic level, wherein the second memory block remains in the long write test mode until selected again, wherein placing the first memory block into the long write test mode followed by placing the second memory block into the long write test mode constitutes a "domino" style entry into the long write test mode.

Claim 36

A structure for performing long write testing of a memory chip comprising: a memory chip divided into a plurality of memory blocks, with each memory block of the plurality of memory blocks having a plurality of memory cells, a plurality of rows, a plurality of columns, a plurality of wordlines, a plurality of bitlines true, and a plurality of bitlines complement; a plurality of block select signals, with each block select signal associated with a memory block; means, associated with a first memory block of the plurality of memory blocks, for placing the first memory block of the plurality of memory blocks into a long write test mode upon selecting the first memory block, and turning off the plurality of wordlines of the first memory block and forcing at least the bitlines true or the bitlines complement of the first memory block to a low logic level wherein the first memory; block remains in the long write test mode until selected again; and means, associated with a second memory block of the plurality of memory blocks, for placing the second memory block of the plurality of memory blocks into the long write test mode upon selecting the second memory block, and turning off the plurality of wordlines of the second memory block and forcing at least the bitlines true or the bitlines complement of the second memory block to the low logic level, wherein the second memory block remains in the long write test mode until selected again, wherein placing the first memory block into the long write test mode followed by placing the second memory block into the long write test mode constitutes a "domino" style entry into the long write test mode.

Claim 37

The structure of claim 33, wherein in placing the first memory block into the long write test mode, also turning on the plurality of columns within the first memory block and in placing the second memory block into the long write test mode, also turning on the plurality of the second memory block.

Claim 38

The structure of claim 33, wherein, in placing the first memory block and the second memory block into the long write test mode, the bitlines true of the first memory block and the bitlines true of the second memory block are forced to the low logic level.

Claim 39

The structure of claim 33, wherein, in placing the first memory block and the second memory block into the long write test mode, the bitlines true and the bitlines complement of the first memory block and the bitlines true and the bitlines complement of the second memory block are forced to the low logic level.

Claim 40

The structure of claim 33, wherein all of the plurality of memory blocks of the memory chip are placed into the long write test mode.

Claim 41

The structure of claim 33, wherein the memory chip is a Static Random Access Memory (SRAM).

Claim 42

The structure of claim 33, wherein each memory block of the plurality of memory blocks remains in the long write test mode until selected again.

Claim 43

The structure of claim 33, wherein a plurality of bitline load elements are connected to the plurality of bitlines true and bitlines complement of the first memory block and the bitline load elements of the first memory block are turned off when the first memory block is placed in the long write test mode, and wherein a plurality of bitline load elements are connected to the plurality of bitlines true and bitlines complement of the second memory block and the bitline load elements of the second memory block are turned off when the second memory block is placed in the long write test mode.

Claim 44

The structure of claim 33, wherein after the step of placing the first memory block and the second memory block of the plurality of memory blocks into the long write test mode, comprising the further steps of: exiting the first memory block of the plurality of memory blocks from the long write test mode by reselecting the first memory block; placing the first memory block of the plurality of memory blocks into a read disturb test mode upon selecting the first memory block, and allowing the wordlines of the first memory block to be enabled and not forcing the bitlines true or the bitlines complement of the first memory block to the low logic level, wherein the first memory block of the plurality of memory blocks remains in the read disturb test mode while selected; exiting the second memory block of the plurality of memory blocks from the long write test mode by reselecting the second memory block; and placing the second memory block of the plurality of memory blocks into the read disturb test mode upon selecting the second memory block, and allowing the wordlines of the second memory block to be enabled and not forcing the bitlines true or the bitlines complement of the second memory block to the low logic level, wherein the second memory block of the plurality of memory blocks remains in the read disturb test mode while selected, wherein placing the first memory block into the read disturb test mode followed by placing the second memory block into the read disturb test-mode constitutes a "domino" style entry into the read disturb test mode.

Claim 45

The structure of claim 41, wherein after the steps of placing the first memory block and the second memory block of the plurality of memory blocks into the long write test mode and before the step of placing the first memory block of the plurality of memory blocks into the read disturb mode, comprising the additional step of: performing a pause to cause a long write disturb of the memory chip.

Claim 46

The structure of claim 41, wherein all of the plurality of memory blocks of the memory chip are placed into the read disturb test mode.

Claim 47

The structure of claim 33, wherein the means for placing each memory block of the plurality of memory blocks into the long write test mode comprises: a logic element, which has a block select signal as a first input signal and a delay signal as a second input signal and which produces a pulsed clock signal; a delay element, which has the block select signal as an input signal and which produces the delay signal as an output signal; a first clocked Flip Flop which receives a long write signal as a first input signal, the pulsed clocked signal as a second input signal used for clocking the first clocked Flip Flop, and produces a first output signal; and a second clocked Flip Flop which receives the first output signal of the first clocked Flip Flop as a first input signal, the pulsed clocked signal as a second input signal used for clocking the second clocked Flip Flop, and produces a second output signal.

Claim 48

The structure of claim 44, wherein the first output signal, the second output signal, and the block select signal are utilized by block row enable circuitry to generate an output signal capable of enabling the rows of a memory block of the plurality of memory blocks.

Claim 49

The structure of claim 44, wherein the first output signal, the second output signal, and the block select signal are utilized by block column enable circuitry to generate an output signal capable of enabling the columns of a memory block of the plurality of memory blocks.

Claim 50

The structure of claim 44, wherein the first output signal, the second output signal, the block select signal, and an edge transition detection signal are utilized by block edge transition detection circuitry to generate an output signal capable of detecting the edge transition of an input signal of the memory chip and communicating this detection to the memory block.

Claim 51

The structure of claim 44, wherein the first output signal, the second output signal, the block select signal, and a write signal are utilized by block write enable circuitry to generate an output signal capable of enabling write control of a memory block of the plurality of memory blocks.